VIRTUALIZATION ACROSS PHYSICAL PARTITIONS OF A MULTI-CORE PROCESSOR (MCP)

• US 20100082942A1
• Filed: 09/30/2008
• Published: 04/01/2010
• Est. Priority Date: 09/30/2008
• Status: Active Grant

• Current Assignee: Kyndryl Incorporated (Kyndryl Holdings, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Hofstee, Harm P., Kim, Moon J., Kim, Daeik, Duvalsaint, Karl J.
• Granted Patent: US 8,732,716 B2
• Time in Patent Office: Days
• US Class Current: 712/30
• CPC Class Codes: G06F 9/45533 Hypervisors; Virtual machine monitors
• CPC Class Codes: G06F 9/5077 Logical partitioning of resources; Management or configuration of virtualized resources specific details on emulation or internal functioning of virtual machines G06F9/455
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Among other things, the disclosure is applied to a generic microprocessor architecture with a set (e.g., one or more) of controlling/main processing elements (e.g., MPEs) and a set of groups of sub-processing elements (e.g., SPEs). Under this arrangement, MPEs and SPEs are organized in a way that a smaller number MPEs control the behavior of a group of SPEs using program code embodied as a set of virtualized control threads. The apparatus includes a MCP coupled to a power supply coupled with cores to provide a supply voltage to each core (or core group) and controlling-digital elements and multiple instances of sub-processing elements. In accordance with these features, virtualized control threads can traverse the physical boundaries of the MCP to control SPE(s) (e.g., logical partitions having one or more SPEs) in a different physical partition (e.g., different from the physical partition from which the virtualized control threads originated.

Claims

1. A multi-core processor, comprising:

a first physical partition comprising a first main processing element, and a first logical partition of sub processing elements;

a second physical partition comprising a second main processing element; and

a first virtualized control thread associating the second main processing element of the second physical partition with the sub-processing elements of the first logical partition.

2. The multi-core processor of claim 1, further comprising a second virtualized control thread associating the second main processing element with a group of sub-processing elements.

3. The multi-core processor of claim 2, the group of sub-processing elements being in the second physical partition.

4. The multi-core processor of claim 2, the group of sub-processing elements being in a third physical partition.

5. The multi-core processor of claim 1, the first logical partition comprising all sub-processing elements in the first physical partition.

6. The multi-core processor of claim 1, the first logical partition comprising only a subset of all sub-processing elements in the first physical partition.

7. The multi-core processor of claim 1, the first virtualized control thread being configured to send program code and data to the sub-processing elements of the first logical partition.

8. The multi-core processor of claim 1, the first virtualized control thread being further configured to collect computation results from the sub-processing elements of the first logical partition.

9. The multi-core processor of claim 1, the first virtualized control thread controlling a clock speed, power consumption and computation loading of the sub-processing elements of the first logical partition.

10. A multi-core processor, comprising:

a first physical partition comprising a first main processing element, and a first group of sub processing elements;

a second physical partition comprising a second main processing element and a second group of sub-processing elements;

a logical partition comprising a third group of sub-processing elements; and

a virtualized control thread associating the second main processing element of the second physical partition with the first logical partition.

11. The multi-core processor of claim 10, the logical partition being in the first physical partition.

12. The multi-core processor of claim 10, the virtualized control thread extending across physical boundaries defined by the first physical partition and the second physical partition.

13. The multi-core processor of claim 10, the virtualized control thread being operable to control the third group of sub-processing elements in the logical partition.

14. The multi-core processor of claim 10, the virtualized control thread being configured to send program code and data to the third group of sub-processing elements of the logical partition.

15. The multi-core processor of claim 10, the virtualized control thread being further configured to collect computation results from the third group of sub-processing elements of the logical partition.

16. The multi-core processor of claim 10, the virtualized control thread controlling a clock speed, power consumption and computation loading of the third group of sub-processing elements of the logical partition.

17. A processing method, comprising:

associating a main processing element of a first physical partition with a logical partition comprising sub-processing elements using a virtualized control thread; and

controlling the group of sub-processing elements using the virtualized control thread.

18. The processing method of claim 18, the virtualized control thread being in the first physical partition, and the logical partition being in the first physical partition.

19. The processing method of claim 18, the virtualized control thread being in a second physical partition, and the logical partition being in the first physical partition.

20. The processing method of claim 18, the virtualized control thread being in the first physical partition and the logical partition being in a second physical partition.

21. A method for deploying a processing system, comprising:

providing a multi-core processor, comprising;

a first physical partition comprising a first main processing element, and a first logical partition of sub processing elements;

a second physical partition comprising a second main processing element; and

a first virtualized control thread associating the second main processing element of the second physical partition with the sub-processing elements of the first logical partition.