DYNAMIC RECONFIGURATION SUPPORT APPARATUS, DYNAMIC RECONFIGURATION SUPPORT METHOD, AND COMPUTER PRODUCT

• US 20100082943A1
• Filed: 09/23/2009
• Published: 04/01/2010
• Est. Priority Date: 09/26/2008
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: YAMAMOTO, Tatsuya
• Granted Patent: US 8,495,339 B2
• Time in Patent Office: Days
• US Class Current: 712/43
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An apparatus controls a circuit having rewritable processor elements and includes an acquiring unit that acquires information concerning a first task under execution by the circuit; a reading unit that, when the information concerning the first task is acquired, reads from a memory, a completion time of the first task; a first calculating unit that calculates a deadline time using the read completion time; an identifying unit that refers to scheduling information in the memory and identifies for a second task, the quantity of processor elements to be rewritten by the deadline time; a second calculating unit that divides the identified quantity of the processor elements by the deadline time to calculate the quantity of processor elements to be rewritten per unit time; and an executing unit that causes the circuit to rewrite the processor elements for the second task, in the quantity per unit time calculated.

Claims

1. A computer-readable recording medium storing therein a dynamic-reconfiguration support program that causes a computer controlling a dynamically reconfigurable circuit comprising a plurality of rewritable processor elements to execute:

acquiring information concerning a first task that is under execution by the dynamically reconfigurable circuit;

reading an execution completion time of the first task, when the information concerning the first task is acquired at the acquiring, the execution completion time being read from a memory storing therein a sequence of tasks to be executed by the dynamically reconfigurable circuit, an execution completion time for each of the tasks, and scheduling information including a quantity of processor elements to be used for each of the tasks;

calculating, using the execution completion time for the first task read at the reading, a deadline time that is a time after which a second task is started by the dynamically reconfigurable circuit;

identifying, by referring to the quantity of processor elements to be used for each of the tasks included in the scheduling information, the quantity of the processor elements that are for the second task and are to be rewritten by the deadline time calculated at the calculating;

calculating the quantity of the processor elements to be rewritten per unit time, by dividing, by the deadline time, the quantity of the processor elements identified at the identifying; and

causing the dynamically configurable circuit to execute, in the quantity per unit time calculated at the calculating of the quantity, rewriting of the processor elements that are for the second task and are to be rewritten by the deadline time.

2. The computer-readable recording medium according to claim 1, the dynamic-reconfiguration support program further causing the computer to execute:

calculating an estimated value of remaining power of a battery that drives the dynamically reconfigurable circuit; and

calculating a threshold value function expressing temporal variation of a threshold indicative of consumable power for the dynamically reconfigurable circuit, wherein

the acquiring includes acquiring from the dynamically reconfigurable circuit, information concerning remaining power of the battery and power consumption information of the dynamically reconfigurable circuit,

the calculating of the estimated value of the remaining power includes calculating the estimated value of the remaining power of the battery up to the deadline time, using the information concerning the remaining power and the scheduling information acquired at the acquiring,

the calculating of the threshold value function includes calculating the threshold value function by substituting, at each predetermined time period, the power consumption information for the estimated value calculated at the calculating of the estimated-value, and

the calculating of the quantity of the processor elements to be rewritten per unit time includes calculating the quantity of the processor elements to be rewritten per unit time by dividing the quantity of the processor elements identified at the identifying, into a quantity rewritable at a power consumption equal to or less than a value of the threshold value function for each unit time.

3. The computer-readable recording medium according to claim 2, wherein

the calculating of the estimated value of the remaining power includes calculating the estimated value of the remaining power using an arbitrary function, and

the calculating of the threshold value function includes calculating the threshold value function by substituting the power consumption information into the arbitrary function at each predetermined time period.

4. The computer-readable recording medium according to claim 2, wherein

the calculating of the estimated value of the remaining power includes calculating the estimated value of the remaining power using an arbitrary attenuating function, and

the calculating of the threshold value function includes calculating the threshold value function by substituting the power consumption information into the arbitrary attenuating function at each predetermined time period.

5. The computer-readable recording medium according to claim 2, wherein

the calculating of the threshold value function includes determining a function expressing the estimated value of the remaining power as the value of the threshold value function, when a power value indicated by the information concerning the remaining power of the battery at the predetermined time is higher than the estimated value of the remaining power.

6. The computer-readable recording medium according to claim 2, the dynamic-reconfiguration support program further causing the computer to execute:

calculating an estimated temperature variation of the battery; and

correcting, using the estimated temperature variation calculated at the calculating of the estimated temperature variation, the quantity of processor elements calculated at the calculating of the quantity of the processor elements to be rewritten per unit time, wherein

the acquiring includes acquiring temperature information of the battery,

the calculating of the estimated temperature variation includes acquiring a variation amount indicated by the temperature information of the battery acquired at the acquiring, the variation amount being an amount of variation at each predetermined time period, and calculating an estimated temperature of the battery during a subsequent predetermined time period by making a temperature indicated by the temperature information of the battery be proportional to the variation amount, and

the correcting includes correcting the quantity of the processor elements calculated at the calculating the quantity of the processor elements to be rewritten per unit time, based on a result of comparison of power output by the battery according to the estimated temperature variation calculated at the calculating the estimated temperature variation and the value of the threshold value function.

7. The computer-readable recording medium according to claim 6, wherein

the correcting includes increasing the quantity of the processor elements calculated at the calculating of the quantity of the processor elements to be rewritten per unit time, when power output by the battery is high based on a ratio, and decreasing the quantity of the processor elements calculated at the calculating of the quantity of the processor elements to be rewritten per unit time, when the power output by the battery is low based on the ratio.

8. A dynamic-reconfiguration support apparatus that controls a dynamically reconfigurable circuit comprising a plurality of rewritable processor elements, the dynamic-reconfiguration support apparatus comprising:

an acquiring unit that acquires information concerning a first task that is under execution by the dynamically reconfigurable circuit;

a reading unit that reads an execution completion time of the first task, when the information concerning the first task is acquired by the acquiring unit, the execution completion time being read from a memory storing therein a sequence of tasks to be executed by the dynamically reconfigurable circuit, an execution completion time for each of the tasks, and scheduling information including a quantity of processor elements to be used for each of the tasks;

a first calculating unit that, using the execution completion time for the first task read by the reading unit, calculates a deadline time that is a time after which a second task is started by the dynamically reconfigurable circuit;

an identifying unit that, by referring to the quantity of processor elements to be used for each of the tasks included in the scheduling information, identifies the quantity of the processor elements that are for the second task and are to be rewritten by the deadline time calculated by the first calculating unit;

a second calculating unit that calculates the quantity of the processor elements to be rewritten per unit time, by dividing, by the deadline time, the quantity of the processor elements identified by the identifying unit; and

an executing unit that causes the dynamically configurable circuit to execute, in the quantity per unit time calculated by the second calculating unit, rewriting of the processor elements that are for the second task and are to be rewritten by the deadline time.

9. A dynamic-reconfiguration support method of controlling a dynamically reconfigurable circuit comprising a plurality of rewritable processor elements, the dynamic-reconfiguration support method comprising:

acquiring information concerning a first task that is under execution by the dynamically reconfigurable circuit;

reading an execution completion time of the first task, when the information concerning the first task is acquired at the acquiring, the execution completion time being read from a memory storing therein a sequence of tasks to be executed by the dynamically reconfigurable circuit, an execution completion time for each of the tasks, and scheduling information including a quantity of processor elements to be used for each of the tasks;

calculating, using the execution completion time for the first task read at the reading, a deadline time that is a time after which a second task is started by the dynamically reconfigurable circuit;

identifying, by referring to the quantity of processor elements to be used for each of the tasks included in the scheduling information, the quantity of the processor elements that are for the second task and are to be rewritten by the deadline time calculated at the calculating;

calculating the quantity of the processor elements to be rewritten per unit time, by dividing, by the deadline time, the quantity of the processor elements identified at the identifying; and

causing the dynamically configurable circuit to execute, in the quantity per unit time calculated at the calculating of the quantity, rewriting of the processor elements that are for the second task and are to be rewritten by the deadline time.