RECOVERY APPARATUS FOR SOLVING BRANCH MIS-PREDICTION AND METHOD AND CENTRAL PROCESSING UNIT THEREOF

• US 20100082953A1
• Filed: 09/30/2008
• Published: 04/01/2010
• Est. Priority Date: 09/30/2008
• Status: Active Grant

• Current Assignee: Faraday Technology Corp.
• Original Assignee: Faraday Technology Corp.
• Inventors: Chiu, Chih-Yung
• Granted Patent: US 7,945,767 B2
• Time in Patent Office: Days
• US Class Current: 712/239
• CPC Class Codes: G06F 9/3844 using dynamic branch prediction, e.g. using branch history tables
• CPC Class Codes: G06F 9/3863 using multiple copies of the architectural state, e.g. shadow registers

Abstract

A recovery apparatus for solving a branch mis-prediction, and a method and a central processing unit (CPU) thereof are provided. The recovery apparatus includes an instruction buffer, at least one circular instruction buffer, and a decoding and pairing circuit. The decoding and pairing circuit is coupled to the instruction buffer and the circular instruction buffer. The instruction buffer stores a plurality of instructions, and the circular instruction buffer stores a recovery instruction queue corresponding to the instructions, wherein the recovery instruction queue includes a plurality of recovery instructions. The decoding and pairing circuit decodes and pairs the instructions and the recovery instructions. When the branch mis-prediction occurs, the decoding and pairing circuit outputs the recovery instructions to an instruction execution and processing circuit which is externally connected to the decoding and pairing circuit.

Claims

1. A recovery apparatus for solving a branch mis-predication, the recovery apparatus comprising:

an instruction buffer, for storing a plurality of instructions;

at least one circular instruction buffer, for storing a recovery instruction queue corresponding to the instructions, wherein the recovery instruction queue comprises a plurality of recovery instructions; and

a decoding and pairing circuit, coupled to the instruction buffer and the circular instruction buffer for decoding and pairing the instructions and the recovery instructions, wherein when the branch mis-predication occurs, the decoding and pairing circuit outputs the recovery instructions to an instruction execution and processing circuit connected to the decoding and pairing circuit externally.

2. The recovery apparatus according to claim 1, wherein the decoding and pairing circuit outputs the instructions to the instruction execution and processing circuit if the branch mis-predication does not occur.

3. The recovery apparatus according to claim 1, further comprising:

a branch target buffer (BTB), for detecting whether a branch prediction occurs, wherein the BTB sends a target program counter (target PC) to a cache controller when the branch prediction occurs;

the cache controller, coupled to the BTB, for controlling an instruction cache memory circuit according to the target PC to fetch the instructions and the recovery instructions stored in the instruction cache memory circuit; and

the instruction cache memory circuit, coupled to the cache controller, the circular instruction buffer, and the instruction buffer, for storing the instructions and the recovery instructions.

4. The recovery apparatus according to claim 1, wherein a number of the recovery instructions which can be stored in the circular instruction buffer is equal to a number of the instructions which can be executed by the instruction execution and processing circuit.

5. The recovery apparatus according to claim 1, wherein the decoding and pairing circuit further sets a branch mis-predication bit of each of the recovery instructions to be 1 and records a branch program counter of each of the recovery instructions.

6. A recovery method for solving a branch mis-predication, the recovery method comprising:

receiving a plurality of instructions into an instruction buffer memory, and receiving a plurality of recovery instructions corresponding to the instructions into at least one circular instruction buffer memory;

encoding and pairing the instructions and the recovery instructions; and

outputting the recovery instructions to an instruction execution and processing circuit when the branch mis-predication occurs.

7. The recovery method according to claim 6, further comprising:

setting a branch mis-predication bit of each of the recovery instructions to be 1, and recording a branch program counter of each of the recovery instructions.

8. The recovery method according to claim 6, further comprising:

outputting the instructions to the instruction execution and processing circuit if the branch mis-predication does not occur.

9. The recovery method according to claim 6, wherein a number of the recovery instructions which can be stored in the circular instruction buffer is equal to a number of the instructions which can be executed by the instruction execution and processing circuit.

10. A central processing unit (CPU) having a recovery apparatus, the CPU comprising:

an instruction buffer, for storing a plurality of instructions;

at least one circular instruction buffer, for storing a recovery instruction queue corresponding to the instructions, wherein the recovery instruction queue comprises a plurality of recovery instructions;

a decoding and pairing circuit, coupled to the instruction buffer and the circular instruction buffer, for decoding and pairing the instructions and the recovery instructions, the decoding and pairing circuit outputting the recovery instructions to an instruction execution and processing circuit when a branch mis-predication occurs; and

the instruction execution and processing circuit, coupled to the decoding and pairing circuit, for executing the recovery instructions and the instructions.

11. The CPU according to claim 10, wherein the decoding and pairing circuit outputs the instructions to the instruction execution and processing circuit if the branch mis-predication does not occur.

12. The CPU according to claim 10, further comprising:

a BTB, for detecting whether a branch prediction occurs, the BTB sending a target PC to a cache controller when the branch prediction occurs;

the cache controller, coupled to the BTB, for controlling a instruction cache memory circuit according to the target PC to fetch the instructions and the recovery instructions stored in the instruction cache memory circuit; and

the instruction cache memory circuit, coupled to the cache controller, the circular instruction buffer, and the instruction buffer, for storing the instructions and the recovery instructions.

13. The CPU according to claim 10, wherein a number of the recovery instructions which can be stored in the circular instruction buffer is equal to a number of the instructions which can be executed by the instruction execution and processing circuit.

14. The CPU according to claim 10, wherein the decoding and pairing circuit further sets a branch mis-predication bit of each of the recovery instructions to be 1 and records a branch program counter of each of the recovery instructions.