POWER MANAGEMENT FOR PROCESSING UNIT

• US 20100083009A1
• Filed: 09/30/2008
• Published: 04/01/2010
• Est. Priority Date: 09/30/2008
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Luria, Kosta, Baum, Dan, Rotem, Efraim, Rajwan, Doron, Korner, Ronny, Vikinski, Omer
• Granted Patent: US 8,386,807 B2
• Time in Patent Office: Days
• US Class Current: 713/300
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode

Abstract

Methods, apparatuses, and systems for managing power of a processing unit are described herein. Some embodiments include determining a voltage variation of a subset of current components of a current consumed by a processing unit. Other embodiments include detecting architectural events on a processing core of the processing unit and instituting various actions to reduce an input rate of instructions to the core. Other embodiments may be described and claimed.

Claims

1. An apparatus comprising:

a processing unit; and

a power management unit coupled to, or integrated within, the processing unit and configured to determine a voltage variation that corresponds to a subset of current components of a current consumed by the processing unit and configured to control a voltage regulator based at least in part on the determined voltage variation.

2. The apparatus of claim 1, wherein the subset of current components has direct current characteristics and the power management unit is further configured to determine another voltage variation that corresponds to another subset of current components, the another subset of current components having alternating current characteristics.

3. The apparatus of claim 1, wherein the subset includes one or more current components and the voltage variation is based at least in part on a magnitude of the one or more current components and an impact value associated with the subset.

4. The apparatus of claim 1, wherein the power management unit is further configured to determine a plurality of voltage variations that respectively correspond to a plurality of subsets of current components of the current.

5. The apparatus of claim 4, wherein the subset is a first subset of the plurality of subsets and is associated with a first impact value and a second subset of the plurality of subsets is associated with a second impact value that is different from the first impact value.

6. The apparatus of claim 5, wherein the first subset includes idle current and/or leakage current and the second subset includes dynamic current.

7. The apparatus of claim 4, wherein the power management unit is further configured to determine an operating condition of the processing unit;

and to determine a magnitude for at least a first and a second subset of the plurality of subsets based at least in part on the determined operating condition.

8. The apparatus of claim 7, wherein the operating condition of the processing unit includes temperature, state of one or more cores of the processing unit, and/or activity of the processing unit.

9. The apparatus of claim 1, wherein the power management unit is further configured to determine the voltage variation based at least in part on a power characteristic of the subset.

10. The apparatus of claim 9, further comprising:

a power characteristic block coupled to the power management unit and configured to provide the power characteristic.

11. An apparatus comprising:

a power management unit; and

a processing core having a detector coupled to the power management unit and configured to detect one or more architectural events of the processing core to be used as at least a partial basis for instituting an action to limit current consumed by the processing core.

12. The apparatus of claim 11, wherein the detector is further configured to institute the action.

13. The apparatus of claim 12, wherein the detector is further configured to communicate detection of the one or more architectural events and/or the institution of the action to the power management unit.

14. The apparatus of claim 13, wherein a voltage admitted to the apparatus is increased based at least in part on the communicated detection of the one or more architectural events and/or the institution of the action to the power management unit and the detector is further configured to cease the action based at least in part on the increased admitted voltage.

15. The apparatus of claim 11, wherein the one or more architectural events include operation of a predetermined number of execution units of the processing core for a predetermined period of time.

16. The apparatus of claim 11, wherein the detected one or more architectural events correspond to a consumption of a predetermined level of current by the processing core.

17. The apparatus of claim 11, wherein the action includes reducing an input rate of instructions to the processing core.

18. The apparatus of claim 11, further comprising:

a plurality of processing cores, including the processing core, each of the plurality of processing cores having a respective detector configured to detect one or more architectural events occurring in a respective processing core to be used as at least a partial basis for instituting an action to limit current consumed by the respective processing core.

19. A machine-accessible medium having associated instructions that, when executed, result in the machine:

reading power characteristics of a subset of current components of a current consumed by a processing unit;

determining a magnitude for the subset based at least in part on the power characteristics;

determining a voltage variation that corresponds to the subset based at least in part on the magnitude of the subset and the power characteristics; and

setting a voltage based at least in part on the determined voltage variation.

20. The machine-accessible medium of claim 19, wherein said determining the magnitude for the subset includes:

determining an operating condition of the processing unit.

21. The machine-accessible medium of claim 19, wherein said instructions, when executed, further result in the machine:

determining another voltage variation that corresponds to another subset of current components of the current; and

setting the voltage based at least further in part on the another voltage variation.

22. A method comprising:

detecting one or more architectural events on a core of a processing unit; and

instituting an action that decreases an input rate of instructions to the core based at least in part on said detecting.

23. The method of claim 22, further comprising:

setting a first voltage for the processing unit;

setting a second voltage for the processing unit based at least in part on said detecting; and

ceasing the action based at least in part on said setting of the second voltage.

24. The method of claim 22, wherein said detecting of the one or more architectural events is performed by a detector on the processing unit.

25. The method of claim 22, wherein the method further comprises:

detecting one or more architectural events on another core of the processing unit; and

instituting an action that decreases an input rate of instructions to the another core based at least in part on said detecting.