Voltage stabilization for clock signal frequency locking

• US 20100083021A1
• Filed: 09/29/2008
• Published: 04/01/2010
• Est. Priority Date: 09/29/2008
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Herrera, Ivan, Allarey, Jose, Jahagirdar, Sanjeev
• Granted Patent: US 8,122,270 B2
• Time in Patent Office: Days
• US Class Current: 713/330
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/30 Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations for resetting only G06F1/24

Abstract

A processor, system, and method are disclosed. In an embodiment, the processor includes a first site and a second site. There is a link to transmit a voltage stabilization signal from the second site to the first site. In the first site voltage correction logic can dynamically modify a voltage supplied to the first site and second site. In the second site there is logic to assert the voltage stabilization signal. After asserting the voltage stabilization signal, the second site is granted at least a window of time in which the supplied voltage to the second site does not change.

Claims

1. A processor, comprising:

a first site and a second site;

a link to transmit a voltage stabilization signal from the second site to the first site;

voltage correction logic in the first site, coupled to the link, to dynamically modify a voltage supplied to the first site and second site; and

logic within the second site, coupled to the link, to assert the voltage stabilization signal,

wherein the second site is granted at least a window of time after asserting the voltage stabilization signal in which the supplied voltage to the second site does not change.

2. The processor of claim 1, further comprising:

clock signal generation logic in the second site to supply a clock signal at one of a plurality of frequencies for the second site.

3. The processor of claim 2, further comprising:

the clock signal generation logic to lock the clock signal at a first frequency during the window of time in which the supplied voltage to the second site does not change.

4. The processor of claim 3, wherein the second site includes logic to:

wait a first period of time after asserting the voltage stabilization signal while the supplied voltage stabilizes; and

allow the clock signal generation logic to begin locking the clock signal at the first frequency after the first period of time.

5. The processor of claim 4, wherein the second site includes logic to deassert the voltage stabilization signal when the clock signal has locked at the first frequency.

6. The processor of claim 1, wherein each site has one or more processor cores.

7. The processor of claim 1, wherein both the first site and second site reside on a single voltage plane.

8. The processor of claim 1, further comprising:

logic within the first site to assert the voltage stabilization signal,

wherein the first site is granted at least the window of time after asserting the voltage stabilization signal in which the supplied voltage to the first site does not change.

9. A system, comprising:

a multi-site processor, each with at least two cores;

a link to transmit a voltage stabilization signal from a second site in the multi-site processor to a first site in the multi-site processor;

voltage correction logic in the first site, coupled to the link, to dynamically modify a voltage supplied to the first site and second site; and

logic within the second site, coupled to the link, to assert the voltage stabilization signal,

wherein the second site is granted at least a window of time after asserting the voltage stabilization signal in which the supplied voltage to the second site does not change.

10. The system of claim 9, further comprising:

clock signal generation logic in the second site to supply a clock signal at one of a plurality of frequencies for the second site.

11. The system of claim 10, further comprising:

the clock signal generation logic to lock the clock signal at a first frequency during the window of time in which the supplied voltage to the second site does not change.

12. The system of claim 11, wherein the second site includes logic to:

wait a first period of time after asserting the voltage stabilization signal while the supplied voltage stabilizes; and

allow the clock signal generation logic to begin locking the clock signal at the first frequency after the first period of time.

13. The system of claim 12, wherein the second site includes logic to deassert the voltage stabilization signal when the clock signal has locked at the first frequency.

14. The system of claim 9, wherein each site has one or more processor cores.

15. The system of claim 9, wherein both the first site and second site reside on a single voltage plane.

16. The system of claim 9, further comprising:

logic within the first site to assert the voltage stabilization signal,

wherein the first site is granted at least the window of time after asserting the voltage stabilization signal in which the supplied voltage to the first site does not change.

17. A method, comprising:

transmitting a voltage stabilization signal from a second site on a multi-site processor to a first site on the multi-core processor, wherein the first site dynamically modifies a voltage supplied to the first site and the second site;

granting the second site at least a window of time after the assertion of the voltage stabilization signal in which the supplied voltage to the second site does not change.

18. The method of claim 17, further comprising:

supplying a clock signal at one of a plurality of frequencies for the second site.

19. The method of claim 18, further comprising:

locking the clock signal at a first frequency of the plurality of frequencies during the window of time in which the supplied voltage to the second site does not change.

20. The method of claim 19, further comprising:

waiting a first period of time after the assertion of the voltage stabilization signal while the supplied voltage stabilizes; and

allowing the clock signal to begin a locking process at the first frequency after the first period of time.

21. The method of claim 20, further comprising:

deasserting the voltage stabilization signal when the clock signal has completed the locking process at the first frequency.

22. The method of claim 17, wherein each site has one or more processor cores.

23. The method of claim 17, wherein both the first site and second site reside on a single voltage plane.

24. The method of claim 17, further comprising:

asserting the voltage stabilization signal from the first site,

wherein the first site is granted at least the window of time after asserting the voltage stabilization signal in which the supplied voltage to the first site does not change.