PHASE SHIFTER WITH REDUCED LINEAR DEPENDENCY

• US 20100083063A1
• Filed: 12/08/2009
• Published: 04/01/2010
• Est. Priority Date: 11/23/1999
• Status: Active Grant

• Current Assignee: Siemens Industry Software Limited (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Tyszer, Jerzy, Rajski, Janusz, Tamarapalli, Nagesh
• Granted Patent: US 7,805,651 B2
• Time in Patent Office: Days
• US Class Current: 714/726
• CPC Class Codes: G01R 31/31813 Test pattern generators
• CPC Class Codes: G01R 31/318385 Random or pseudo-random test pattern
• CPC Class Codes: G01R 31/318541 Scan latches or cell details
• CPC Class Codes: G01R 31/318547 Data generators or compressors
• CPC Class Codes: G01R 31/318594 Timing aspects clock circuits G01R31/318552

Abstract

A method is disclosed for the automated synthesis of phase shifters—circuits used to remove effects of structural dependencies featured by pseudo-random test pattern generators driving parallel scan chains. Using a concept of duality, the method relates the logical states of linear feedback shift registers (LFSRs) and circuits spacing their inputs to each of the output channels. The method generates a phase shifter network balancing the loads of successive stages of LFSRs and satisfying criteria of reduced linear dependency, channel separation and circuit complexity.

Claims

1-35. -35. (canceled)

36. A built-in-self-test circuit, comprising:

a linear finite state machine including multiple memory elements with at least one feedback connection between the memory elements, the linear finite state machine having multiple outputs with a substantially balanced load on the outputs;

a plurality of scan chains for storing test patterns used to test an integrated circuit;

a phase shifter positioned between the linear finite state machine and the scan chains, the phase shifter including a plurality of inputs coupled in parallel to the multiple outputs of the linear finite state machine.

37. The built-in-self-test circuit of claim 36, wherein the memory elements in the linear finite state machine are flip flops coupled in a ring structure.

38. The built-in-self-test circuit of claim 36, wherein the phase shifter includes XOR gates coupled between the plurality of inputs to reduce correlation of test patterns provided by the linear finite state machine.

39. The built-in-self-test circuit of claim 36, wherein the linear finite state machine can generate output combinations of test patterns with a predetermined interchannel separation.

40. The built-in-self-test circuit of claim 36, wherein the linear finite state machine is a linear feedback shift register or cellular automata.

41. One or more computer-readable media storing circuit design information for implementing the apparatus of claim 36.

42. A method for creating a built-in-self-test circuit, comprising:

generating a linear feedback shift register having multiple flip-flops with outputs of the linear feedback shift register extending from the flip-flops;

generating a phase shifter coupled to the linear feedback shift register by randomly selecting the outputs of the linear feedback shift register for coupling to the phase shifter and checking whether the randomly selected outputs will provide adequate interchannel separation that exceeds a predetermined limit and whether loading on the outputs of the linear feedback shift register is substantially evenly distributed;

coupling outputs of the phase shifter to a plurality of scan chains for storing test patterns generated by the linear feedback shift register and the phase shifter.

43. The method of claim 42, further including simulating the linear finite shift register.

44. The method of claim 42, further including generating test patterns and testing an integrated circuit using the generated test patterns.

45. The method of claim 42, wherein the interchannel separation is at least a length of a longest scan chain.

46. The method of claim 42, wherein the flip-flops are coupled in a ring with intermediate feedbacks coupled to logic gates positioned between the flip-flops.

47. The method of claim 42, wherein the phase shifter includes multiple conductors coupled in parallel to respective outputs of the linear feedback shift register and multiple logic gates coupled between the multiple conductors.

48. The method of claim 47, wherein the logic gate includes XOR gates or XNOR gates.

49. The method of claim 42, further including tracking whether a flip-flop has exceeded a loading limit and excluding the flip-flop as being potentially coupled to the phase shifter.