Multi-thread processor and its hardware thread scheduling method

• US 20100083267A1
• Filed: 09/28/2009
• Published: 04/01/2010
• Est. Priority Date: 09/30/2008
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Oomoto, Teppei, Adachi, Koji
• Granted Patent: US 8,365,179 B2
• Time in Patent Office: Days
• US Class Current: 718/103
• CPC Class Codes: G06F 2209/507 Low-level
• CPC Class Codes: G06F 9/3838 Dependency mechanisms, e.g. register scoreboarding
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/5027 the resource being a machine, e.g. CPUs, Servers, Terminals

Abstract

A multi-thread processor in accordance with an exemplary aspect of the present invention includes a plurality of hardware threads each of which generates an independent instruction flow, a first thread scheduler that outputs a first thread selection signal designating a hardware thread to be executed in the next execution cycle, a first selector that outputs an instruction generated by the selected hardware thread according to the first thread selection signal, and an execution pipeline that executes an instruction output from the first selector, wherein whenever a hardware thread is executed in the execution pipeline, the first thread scheduler updates the priority rank of the executed hardware thread and outputs the first thread selection signal in accordance with the updated priority rank.

Claims

1. A multi-thread processor comprising:

a plurality of hardware threads each of which generates an independent instruction flow;

a first thread scheduler that outputs a first thread selection signal, the first thread selection signal designating a hardware thread to be executed in a next execution cycle among the plurality of hardware threads according to a priority rank, the priority rank being established in advance for each of the plurality of hardware threads;

a first selector that selects one of the plurality of hardware threads according to the first thread selection signal and outputs an instruction generated by the selected hardware thread; and

an execution pipeline that executes an instruction output from the first selector,

wherein whenever the hardware thread is executed in the execution pipeline, the first scheduler updates the priority rank for the executed hardware thread and outputs the first thread selection signal in accordance with the updated priority rank.

2. The multi-thread processor according to claim 1, wherein the first thread scheduler preferentially selects the hardware thread having a high priority rank and outputs the first thread selection signal, and whenever the hardware thread designated by the first thread selection signal is executed in the execution pipeline, decreases the priority rank of that hardware thread.

3. The multi-thread processor according to claim 1, wherein when there are two or more hardware threads having the same priority rank, the first thread scheduler selects one of the hardware threads in accordance with a pre-established rule, and outputs the first thread selection signal designating the selected hardware thread.

4. The multi-thread processor according to claim 1, wherein when there is a high dependency relation between the instruction being executed in the execution pipeline and the instruction prepared in the plurality of hardware threads, the first thread scheduler sets the priority rank of the hardware thread containing the instruction having the high dependency relation at a minimum rank.

5. The multi-thread processor according to claim 1, further comprising:

a second scheduler that specifies execution of at least one hardware thread selected in a fixed manner among the plurality of hardware threads in a predetermined first execution period, and outputs a second thread selection signal specifying execution of an arbitrary hardware thread in a second execution period other than the first execution period and a real-time bit signal indicating one of the first execution period and the second execution period; and

a second selector that receives the real-time bit signal, and when the real-time bit signal indicates the first execution period, provides the second thread selection signal to the first selector, and when the real-time bit signal indicates the second execution period, provides the first thread selection signal to the first selector.

6. The multi-thread processor according to claim 1, wherein

the first thread scheduler comprises:

a plurality of dispatch counters each of which retains a dispatch count value corresponding to a priority rank for the corresponding hardware thread;

a priority rank decision unit that refers dispatch count values retained in the plurality of dispatch counters and determines the hardware thread having a highest priority rank; and

a thread number selection unit that outputs the first thread selection signal designating the hardware thread determined to have the highest priority rank in the priority rank decision unit, and

the plurality of dispatch counters receive a dispatch signal, and when the dispatch signal indicates a hardware thread corresponding to one of the dispatch counters, update the dispatch count value output from that dispatch counter, the dispatch signal being output whenever the hardware thread is executed in the execution pipeline and used to notify of the executed hardware thread.

7. The multi-thread processor according to claim 6, further comprising a initialization decision unit that when dispatch count values retained in the plurality of dispatch counters satisfy a predetermined initialization condition, resets the dispatch count values to initial values.

8. The multi-thread processor according to claim 6, wherein each of the plurality of dispatch counters comprises:

a counter initialization value storage unit that stores a counter initialization value corresponding to a priority rank of the corresponding hardware thread;

a count value storage unit that stores the count initialization value as a initial value of a count value;

a decrementer that receives the dispatch signal and updates the count value stored in the count value storage unit; and

a third selector that receives a mask signal, selects one of the counter value and a mask value corresponding to the count value having a minimum priority rank according to the mask signal, and outputs the selected value as the dispatch count value, the mask signal being output from a pipeline control circuit for the hardware thread containing an instruction having a high dependency relation, the pipeline control circuit being configured to monitor a dependency relation between the instruction being executed in the execution pipeline and the instruction prepared in the plurality of hardware threads.

9. The multi-thread processor according to claim 1, wherein an initial value for priority ranks of the plurality of hardware threads is established by a management program that is executed when the multi-thread processor is started up.

10. A hardware thread scheduling method in a multi-thread processor, the multi-thread processor comprising a plurality of hardware threads and being configured to execute an instruction flow generated by the hardware thread while switching the hardware thread in accordance with a predefined schedule, the hardware thread scheduling method comprising:

selecting a hardware thread having a highest priority rank among the plurality of hardware threads;

executing an instruction generated by the selected hardware thread;

updating the priority rank of the hardware thread that generated the executed instruction; and

selecting the hardware thread having a highest priority rank among the updated priority ranks as the hardware thread that generates an instruction next.

11. The hardware thread scheduling method according to claim 10, wherein the updating of the priority rank comprising decreasing a priority rank of the hardware thread that generated the executed instruction.

12. The hardware thread scheduling method according to claim 10, wherein when there is a high dependency relation between an instruction generated by the plurality of hardware threads and an instruction under execution, the priority rank of the hardware thread containing the instruction having the high dependency relation is set at a minimum rank.