MATCHED MULTIPLIER CIRCUIT HAVING REDUCED PHASE SHIFT FOR USE IN MEMS SENSING APPLICATIONS

• US 20100083754A1
• Filed: 10/02/2008
• Published: 04/08/2010
• Est. Priority Date: 10/02/2008
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Mijuskovic, Dejan, Bien, David E.
• Granted Patent: US 8,082,789 B2
• Time in Patent Office: Days
• US Class Current: 73/504.120
• CPC Class Codes: G01C 19/56 Turn-sensitive devices using vibrating masses, e.g. vibratory angular rate sensors based on Coriolis forces
• CPC Class Codes: G01P 15/13 by measuring the force required to restore a proofmass subjected to inertial forces to a null position
• CPC Class Codes: G06G 7/16 for multiplication or division G06G7/19 and G06G7/24 take precedence; measuring electric power G01R21/00

Abstract

Apparatus and methods are provided for multiplier circuits having reduced phase shift. A multiplier circuit comprises an input node for an input signal and an output node for an output signal. A first multiplier is coupled to the input node and has a first multiplier output, wherein the first multiplier multiplies the input signal by a first signal to produce a second signal at the first multiplier output. A second multiplier is coupled to the output node and is matched to the first multiplier. The second multiplier multiplies the output signal by a third signal to produce a fourth signal at a second multiplier output. An amplifier is coupled to the first multiplier output and the second multiplier output and produces the output signal at an amplifier output coupled to the output node based upon the second signal and the fourth signal.

Claims

1. A multiplier circuit comprising:

an input node for an input signal;

an output node for an output signal;

a first multiplier coupled to the input node, the first multiplier having a first multiplier output, wherein the first multiplier is configured to multiply the input signal by a first signal to produce a second signal at the first multiplier output;

a second multiplier coupled to the output node, the second multiplier being matched to the first multiplier and having a second multiplier output, wherein the second multiplier is configured to multiply the output signal by a third signal to produce a fourth signal at the second multiplier output; and

an amplifier coupled to the first multiplier output and the second multiplier output, the amplifier having an amplifier output coupled to the output node, wherein the amplifier is configured to produce the output signal at the amplifier output based upon the second signal and the fourth signal.

2. The multiplier circuit of claim 1, the amplifier having a first amplifier input, wherein the multiplier circuit further comprises a summing element comprising:

a first summing input coupled to the first multiplier output;

a second summing input coupled to the second multiplier output; and

a summing output coupled to the first amplifier input, wherein the summing element is configured to produce a sum of the second signal and the fourth signal at the summing output and the amplifier produces the output signal based upon the sum.

3. The multiplier circuit of claim 2, wherein the amplifier has a second amplifier input coupled to a reference potential.

4. The multiplier circuit of claim 3, wherein the first amplifier input comprises an inverting input and the second amplifier input comprises a non-inverting input.

5. The multiplier circuit of claim 1, wherein the amplifier has a first input coupled to the first multiplier output and the second multiplier output.

6. The multiplier circuit of claim 5, wherein the amplifier has a second input coupled to a reference potential.

7. The multiplier circuit of claim 6, wherein the first input comprises an inverting input and the second input comprises a non-inverting input.

8. The multiplier circuit of claim 6, further comprising a resistance element coupled between the first input and the reference potential.

9. The multiplier circuit of claim 1, wherein a phase shift of the first multiplier is substantially equal to a phase shift of the second multiplier.

10. A gyroscope for measuring a rate of rotation, the gyroscope comprising:

a mechanical resonator configured to generate a first signal based on movement of the gyroscope and a feedback signal;

a sensing architecture coupled to the mechanical resonator, the sensing architecture being configured to demodulate the first signal using a carrier signal to produce a baseband signal; and

a modulation architecture coupled to the sensing architecture and the mechanical resonator, the modulation architecture comprising;

an amplifier having a first input and an output, wherein the amplifier is configured to produce the feedback signal at the output in response to a second signal at the first input;

a first multiplier having a first multiplier output coupled to the first input of the amplifier, the first multiplier being configured to produce the baseband signal multiplied by the carrier signal at the first multiplier output; and

a second multiplier coupled between the output and the first input of the amplifier, the second multiplier having a second multiplier output coupled to the input of the amplifier, the second multiplier being configured to produce the feedback signal multiplied by a third signal at the second multiplier output;

wherein a transfer function of the second multiplier is substantially matched to a transfer function of the first multiplier.

11. The gyroscope of claim 10, wherein a phase shift of the first multiplier is substantially equal to a phase shift of the second multiplier.

12. The gyroscope of claim 10, wherein a phase shift of the feedback signal relative to the carrier signal is substantially equal to a difference between a phase shift of the first multiplier and a phase shift of the second multiplier.

13. The gyroscope of claim 10, the amplifier having a second input, wherein the second input is coupled to a reference potential.

14. The gyroscope of claim 13, wherein the first input comprises an inverting input and the second input comprises a non-inverting input.

15. The gyroscope of claim 14, further comprising a resistance element coupled between the first input and the reference potential.

16. The gyroscope of claim 10, wherein the modulation architecture further comprises a summing element coupled between the first multiplier, the second multiplier, and the amplifier, the summing element comprising:

a first summing input coupled to the first multiplier output;

a second summing input coupled to the second multiplier output; and

a summing output coupled to the first input of the amplifier, wherein the summing element is configured to produce the second signal at the summing output by adding the product of the baseband signal and the carrier signal and the product of the feedback signal and the third signal.

17. The gyroscope of claim 10, further comprising a driving architecture coupled to the mechanical resonator, the sensing architecture, and the modulation architecture, the driving architecture being configured to determine a resonant frequency of the mechanical resonator, wherein the carrier signal is generated based on the resonant frequency.

18. A method for reducing a phase shift in an output signal relative to a first signal, the method comprising:

multiplying an input signal and the first signal using a first multiplier to obtain a second signal;

generating the output signal based on the second signal and a feedback signal; and

multiplying the output signal and a third signal using a second multiplier to obtain the feedback signal, wherein the second multiplier is configured such that a phase shift of the second multiplier substantially negates a phase shift of the first multiplier.

19. The method of claim 18, wherein generating the output signal based on the second signal and the feedback signal comprises:

determining a difference between the second signal and the feedback signal; and

generating the output signal based on the difference between the second signal and the feedback signal.

20. The method of claim 19, the second multiplier being configured as a negative feedback path for an amplifier configured to generate the output signal, wherein determining the difference between the second signal and the feedback signal comprises:

adding the second signal and the feedback signal to obtain a sum; and

providing the sum to an inverting input of the amplifier.