DISPLAY DEVICE

• US 20100084650A1
• Filed: 09/28/2009
• Published: 04/08/2010
• Est. Priority Date: 10/03/2008
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: AKIMOTO, Kengo, YAMAZAKI, Shunpei, UMEZAKI, Atsushi
• Granted Patent: US 9,324,874 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/42356 Disposition, e.g. buried gate electrode H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A pixel portion and a driver circuit driving the pixel portion are formed over the same substrate. At least a part of the driver circuit is formed using an inverted staggered thin film transistor in which an oxide semiconductor layer is used and a channel protective layer is provided over the oxide semiconductor layer serving as a channel formation region which is overlapped with the gate electrode. The driver circuit as well as the pixel portion is provided over the same substrate to reduce manufacturing costs.

Claims

1. A display device comprising a pixel portion and a driver circuit,

wherein the pixel portion comprises a first thin film transistor including at least a first oxide semiconductor layer and a first channel protective layer in contact with the first oxide semiconductor layer,

wherein the driver circuit comprises a second thin film transistor including at least a second oxide semiconductor layer and a second channel protective layer in contact with the second oxide semiconductor layer and a third thin film transistor including a third oxide semiconductor layer and a third channel protective layer in contact with the third oxide semiconductor layer,

wherein a wiring in direct contact with a gate electrode of the second thin film transistor provided below the second oxide semiconductor layer is provided above the third oxide semiconductor layer, and

wherein the wiring is a source wiring or a drain wiring of the third thin film transistor electrically connected to the third oxide semiconductor layer.

2. The display device according to claim 1, wherein the second thin film transistor is a depletion type transistor and the third thin film transistor is an enhancement type transistor.

3. The display device according to claim 1, wherein the second thin film transistor and the third thin film transistor are enhancement type transistors.

4. The display device according to claim 1, wherein the first oxide semiconductor layer, the second oxide semiconductor layer and the third oxide semiconductor layer comprise indium, gallium and zinc.

5. A display device comprising a pixel portion and a driver circuit,

wherein the pixel portion comprises a first thin film transistor including at least a first oxide semiconductor layer and a first channel protective layer in contact with the first oxide semiconductor layer,

wherein the driver circuit comprises a second thin film transistor including at least a second oxide semiconductor layer and a second channel protective layer in contact with the second oxide semiconductor layer and a third thin film transistor including a third oxide semiconductor layer and a third channel protective layer in contact with the third oxide semiconductor layer,

wherein a wiring in direct contact with a gate electrode of the second thin film transistor provided below the second oxide semiconductor layer is provided above the third oxide semiconductor layer,

wherein the wiring is a source wiring or a drain wiring of the third thin film transistor electrically connected to the third oxide semiconductor layer, and

wherein a fourth oxide semiconductor layer having smaller thickness and higher conductivity than the third oxide semiconductor layer is provided between the source wiring and the third oxide semiconductor layer or between the drain wiring and the third oxide semiconductor layer.

6. The display device according to claim 5, wherein the second thin film transistor is a depletion type transistor and the third thin film transistor is an enhancement type transistor.

7. The display device according to claim 5, wherein the second thin film transistor and the third thin film transistor are enhancement type transistors.

8. The display device according to claim 5, wherein the first oxide semiconductor layer, the second oxide semiconductor layer and the third oxide semiconductor layer comprise indium, gallium and zinc.

9. The display device according to claim 5, wherein the fourth oxide semiconductor layer comprises indium, gallium and zinc.

10. A display device comprising a pixel portion and a driver circuit,

wherein the pixel portion comprises a first thin film transistor including at least a first oxide semiconductor layer and a first channel protective layer in contact with the first oxide semiconductor layer,

wherein the driver circuit comprises a second thin film transistor including at least a second oxide semiconductor layer and a second channel protective layer in contact with the second oxide semiconductor layer and a third thin film transistor including a third oxide semiconductor layer and a third channel protective layer in contact with the third oxide semiconductor layer,

wherein a wiring in direct contact with a gate electrode of the second thin film transistor provided below the second oxide semiconductor layer is provided above the third oxide semiconductor layer,

wherein the wiring is a source wiring or a drain wiring of the third thin film transistor electrically connected to the third oxide semiconductor layer, and

wherein an insulating layer covers the first thin film transistor, the second thin film transistor, and the third thin film transistor and is in contact with the first channel protective layer, the second channel protective layer, and the third channel protective layer.

11. The display device according to claim 10, wherein the second thin film transistor is a depletion type transistor and the third thin film transistor is an enhancement type transistor.

12. The display device according to claim 10, wherein the second thin film transistor and the third thin film transistor are enhancement type transistors.

13. The display device according to claim 10, wherein the first oxide semiconductor layer, the second oxide semiconductor layer and the third oxide semiconductor layer comprise indium, gallium and zinc.

14. A display device comprising a pixel portion and a driver circuit,

wherein the pixel portion comprises a first thin film transistor including at least a first oxide semiconductor layer and a first channel protective layer in contact with the first oxide semiconductor layer,

wherein the driver circuit comprises a second thin film transistor including at least a second oxide semiconductor layer and a second channel protective layer in contact with the second oxide semiconductor layer and a third thin film transistor including a third oxide semiconductor layer and a third channel protective layer in contact with the third oxide semiconductor layer,

wherein a wiring in direct contact with a gate electrode of the second thin film transistor provided below the second oxide semiconductor layer is provided above the third oxide semiconductor layer

wherein the wiring is a source wiring or a drain wiring of the third thin film transistor electrically connected to the third oxide semiconductor layer,

wherein a fourth oxide semiconductor layer having smaller thickness and higher conductivity than the third oxide semiconductor layer is provided between the source wiring and the third oxide semiconductor layer or between the drain wiring and the third oxide semiconductor layer, and

wherein an insulating layer covers the first thin film transistor, the second thin film transistor, and the third thin film transistor and is in contact with the first channel protective layer, the second channel protective layer, and the third channel protective layer.

15. The display device according to claim 14, wherein the second thin film transistor is a depletion type transistor and the third thin film transistor is an enhancement type transistor.

16. The display device according to claim 14, wherein the second thin film transistor and the third thin film transistor are enhancement type transistors.

17. The display device according to claim 14, wherein the first oxide semiconductor layer, the second oxide semiconductor layer and the third oxide semiconductor layer comprise indium, gallium and zinc.

18. The display device according to claim 14, wherein the fourth oxide semiconductor layer comprises indium, gallium and zinc.

19. A display device comprising a pixel portion and a driver circuit,

wherein the pixel portion comprises a first thin film transistor including at least a first oxide semiconductor layer, a first gate electrode, a first gate insulating layer and a first channel protective layer in contact with the first oxide semiconductor layer,

wherein the driver circuit comprises a second thin film transistor including at least a second oxide semiconductor layer, a second gate electrode, a second gate insulating layer and a second channel protective layer in contact with the second oxide semiconductor layer, and

wherein a source wiring or a drain wiring is contact with the second gate electrode through the second gate insulating layer.

20. The display device according to claim 19, wherein the first oxide semiconductor layer and the second oxide semiconductor layer comprise indium, gallium and zinc.