Zigzag Pattern for TSV Copper Adhesion

• US 20100084747A1
• Filed: 10/03/2008
• Published: 04/08/2010
• Est. Priority Date: 10/03/2008
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Kuo, Chen-Cheng, Chen, Chen-Shien, Shen, Wen-Wei, Chen, Chih-Hua
• Granted Patent: US 8,653,648 B2
• Time in Patent Office: Days
• US Class Current: 257/621
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2221/68372 used to support a device or wafer when forming electrical connections thereto
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02311 Additive methods
• CPC Class Codes: H01L 2224/02351 comprising interlocking features
• CPC Class Codes: H01L 2224/05556 in side view
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/525 with adaptable interconnections
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/19041 being a capacitor

Abstract

A system and method for forming a TSV contact is presented. A preferred embodiment includes a TSV in contact with a portion of the uppermost metal layer of a semiconductor die. The interface between the TSV conductor and the contact pad is preferably characterized by a non-planar zigzag pattern that forms a grid pattern of contacts. Alternatively, the contacts may form a plurality of metal lines that make contact with the contact pad.

Claims

1. A semiconductor device comprising:

a substrate with a first conductive feature;

a passivation layer over the first conductive feature; and

a first contact pad extending through multiple openings in the passivation layer to make multiple discontinuous contacts with the first conductive feature.

2. The semiconductor device of claim 1, wherein the discontinuous contacts are discontinuous in a first direction and continuous in a second direction substantially perpendicular to the first direction.

3. The semiconductor device of claim 1, wherein the discontinuous contacts are discontinuous in a first direction and a second direction, the second direction being substantially perpendicular to the first direction.

4. The semiconductor device of claim 3, wherein the discontinuous contacts form a grid pattern.

5. The semiconductor device of claim 1, further comprising a second conductive feature over the first contact pad.

6. The semiconductor device of claim 1, further comprising:

a second conductive feature located within the substrate; and

a second contact pad that extends through the passivation layer and has a substantially planar interface with the second conductive feature.

7. The semiconductor device of claim 1, further comprising a through silicon via electrically connected to the first contact pad.

8. The semiconductor device of claim 7, wherein the first contact pad is located on a first side of the substrate, and the through silicon via contacts a conductor on a second side of the substrate opposite the first side.

9. A semiconductor device comprising:

a semiconductor substrate;

metal layers over the semiconductor substrate;

a passivation layer over the metal layers; and

a first conductor extending through multiple openings in the passivation layer and sharing an interface with an uppermost metal layer, wherein, in a first direction, the first conductor alternates between contacting the uppermost metal layer and the passivation layer.

10. The semiconductor device of claim 9, further comprising a through silicon via extending at least partially through the semiconductor substrate, the through silicon via in contact with the first conductor.

11. The semiconductor device of claim 9, wherein, in a second direction substantially perpendicular with the first direction, the interface is substantially continuous.

12. The semiconductor device of claim 9, wherein, in a second direction substantially perpendicular with the first direction, the first conductor alternates between contacting the uppermost metal layer and the passivation layer.

13. The semiconductor device of claim 12, wherein the interface forms a substantially symmetrical grid pattern of contacts.

14. The semiconductor device of claim 9, further comprising a second conductor different from the first conductor having a substantially planar interface between the second conductor and a portion of the uppermost metal layer.

15. A semiconductor device comprising:

a semiconductor substrate comprising a first metal layer;

a passivation layer over portions of the first metal layer; and

a first conductive layer shaped in a zigzag pattern with a plurality of extensions through the passivation layer to make a plurality of contact points with the first metal layer, the first conductive layer in contact with between about 30% and about 70% of the first metal layer.

16. The semiconductor device of claim 15, further comprising a second conductive layer electrically coupling the first conductive layer to a through silicon via.

17. The semiconductor device of claim 15, wherein the passivation layer forms a series of substantially parallel lines in a first direction between the first metal layer and the first conductive layer.

18. The semiconductor device of claim 15, wherein the passivation layer forms a grid pattern between the first metal layer and the first conductive layer.

19. The semiconductor device of claim 15, further comprising:

a second metal layer in the semiconductor substrate;

a second conductive layer comprising a substantially planar interface with the second metal layer that is substantially parallel with a major surface of the semiconductor substrate.

20. The semiconductor device of claim 15, wherein the first conductive layer is electrically connected to a second conductive layer on an opposite side of the semiconductor substrate than the first conductive layer.