MULTI-PHASE SIGNAL GENERATOR AND METHOD

• US 20100085099A1
• Filed: 10/03/2008
• Published: 04/08/2010
• Est. Priority Date: 10/03/2008
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ma, Yantao
• Granted Patent: US 8,008,954 B2
• Time in Patent Office: Days
• US Class Current: 327/295
• CPC Class Codes: G06F 1/06 Clock generators producing several clock signals G06F1/08 - G06F1/14 take precedence
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled
• CPC Class Codes: H03L 7/0816 the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/10 for assuring initial synchronisation or for broadening the capture range
• CPC Class Codes: H03L 7/1077 by changing characteristics of the phase or frequency detection means H03L7/1072 takes precedence

Abstract

Multi-phase signal generators and methods for generating multi-phase signals are described. In one embodiment, the clock generator generates quadrature clock signals including those having 90, 180, 270 and 360 degrees phase difference with a first clock signal. One of the intermediate clock signals may be used as an enable signal to guide locking of all signals. For example, the 180 degree clock signal may be inverted and used as an enable signal to guide locking of the initial and 360 degree signals in a single phase adjustment procedure. The 0 and 360 degree signals may be delayed before their phase is compared to compensate for duty cycle error in the clock signals.

Claims

1. A multi-phase periodic signal generator comprising:

a plurality of delay elements including a first delay element, an intermediate delay element, and a third delay element, each of the first and second delay elements coupled such that an output of a respective delay element is coupled to an input of a next delay element, each of the respective delay elements configured to delay a signal applied to an input of the respective delay element and couple the delayed signal to the respective next delay element, the first delay element configured to receive a first periodic signal, the intermediate delay element configured to output an intermediate periodic signal, and the last delay element configured to output a third signal;

a phase detector configured to receive the first signal, the last signal, and the intermediate, the phase detector configured to be enabled responsive to the intermediate signal and when enabled to provide a signal indicative of a phase difference between the first and last signals; and

a control signal generator configured to receive the signal indicative of the phase difference between the first and last signals and generate a control signal to adjust the delay of the plurality of delay elements such that the first, intermediate and last signals have a predetermined phase relationship.

2. The multi-phase signal generator according to claim 1 wherein the control signal generator comprises a charge pump configured to receive the signal indicative of the phase difference between the first and last signals and generate a control signal to adjust a delay of each of the plurality of delay elements to minimize the phase difference between the first and last signals.

3. The multi-phase signal generator according to claim 1 further comprising:

a duty cycle distortion tolerance delay element configured to receive the intermediate clock signal and output a delayed intermediate clock signal to the phase detector.

4. The multi-phase signal generator according to claim 1 further comprising:

a duty cycle distortion tolerance delay element configured to receive the first signal and the last clock signal, the duty cycle distortion tolerance delay element configured to delay the respective first and last signals and output the delayed first and last signals to the phase detector.

5. The multi-phase signal generator according to claim 4 wherein the duty cycle distortion tolerance delay element is configured to delay the first and last signals such that rising edges of the first and last signals occur while the phase detector is enabled.

6. The multi-phase signal generator according to claim 4 wherein the duty cycle distortion tolerance delay element comprises a first delay element coupled to the output of the last delay element and a second delay element coupled to the input of the first delay element.

7. The multi-phase signal generator according to claim 6 wherein the phase detector further comprises:

an inverter coupled to receive the intermediate signal and output an inverted intermediate signal; and

a first AND gate coupled to receive the inverted intermediate signal and the delayed first signal, the first AND gate configured to generate a first output signal when the inverted intermediate signal and the delayed first signal have a same logic level; and

a second AND gate coupled to receive the inverted intermediate signal and the delayed last signal, the second AND gate configured to generate a second output signal when the inverted intermediate signal and the delayed last signal have the same logic level.

8. The multi-phase signal generator according to claim 7 wherein the control signal generator comprises:

a charge pump and loop filter configured to receive the first and second output signals and generate a control signal to adjust the delay of the plurality of delay elements to minimize a difference between the first and second output signals.

9. The multi-phase signal generator according to claim 8 wherein the loop filter comprises a capacitance.

10. The multi-phase signal generator according to claim 8 wherein each of the plurality of delay elements includes a control input, each of the respective plurality of delay elements configured to delay the signal applied to its respective control input an amount determined by a signal applied to its respective control input, the multi-phase signal generator further comprising:

a bias generator configured to receive the control signal and couple a bias signal to the control inputs of the plurality of delay elements, the bias signal configured to adjust the delay of the delay elements to minimize the difference between the first and second output signals.

11. The multi-phase signal generator according to claim 10 wherein the plurality of delay elements includes a plurality of groups of delay elements, each group configured to provide a different resolution of signal delay control, the bias generator configured to couple a different bias signals to each respective group of delay elements.

12. The multi-phase signal generator according to claim 1 wherein the intermediate signal has a 180 degree phase difference from the first signal and the last signal has a 360 degree phase difference from the first signal.

13. The multi-phase signal generator according to claim 12 wherein one of the plurality of delay elements is configured to output a signal having a 90 degree phase difference from the first signal and another one of the plurality of delay elements is configured to output a signal having a 270 degree phase difference from the first signal.

14. The multi-phase signal generator according to claim 13 wherein the plurality of delay elements includes a first group of delay elements including the first delay element, the delay elements of the first group coupled in series and configured to output the signal having a 90 degree phase difference from the first signal and wherein the plurality of delay elements includes a second group of delay elements, the delay elements of the second group coupled in series and configured to receive the signal having a 90 degree phase difference from the first signal and output the intermediate signal having a 180 degree phase difference from the first signal, and wherein the plurality of delay elements further includes a third group of delay elements, the delay elements of the third group coupled in series and configured to output the signal having a 270 degree phase difference from the first signal, and wherein the plurality of delay elements further includes a fourth group of delay elements including the third/last element, the delay elements of the fourth group coupled in series and configured to receive the signal having a 270 degree phase difference from the first signal and output the last clock signal having a 360 degree phase difference from the first signal, and wherein the first, second, third and fourth groups of delay elements are configured to provide substantially a same amount of delay responsive to a control signal received from the bias generator.

15. The multi-phase periodic signal generator according to claim 1 wherein the plurality of delay elements each comprise single-ended delay elements.

16. The multi-phase periodic signal generator according to claim 1 wherein the plurality of delay elements each comprise double-ended delay elements.

17. The multi-phase periodic signal generator according to claim 1 wherein the control signal generator is configured to adjust the phase relationship between the first and last signals and the phase relationship between the intermediate and last signals in a single adjustment.

18. The multi-phase periodic signal generator according to claim 1 wherein the phase detector is guided by the intermediate signal.

19. A memory device comprising:

an input buffer configured to receive an input clock signal;

a multi-phase clock signal generator coupled to the input buffer, the multi-phase clock signal generator comprising;

a plurality of delay elements including a first delay element, an intermediate delay element, and a third delay element, each of the first and second delay elements coupled such that an output of a respective delay element is coupled to an input of a next delay element, each of the respective delay elements configured to delay a signal applied to an input of the respective delay element and couple the delayed signal to the respective next delay element, the first delay element configured to receive a first clock signal based on the input clock signal, the intermediate delay element configured to output an intermediate clock signal, and the third delay element configured to output a last clock signal;

a phase detector configured to receive the first clock signal, the last clock signal, and the intermediate clock signal, the phase detector configured to be enabled responsive to the intermediate clock signal and when enabled to provide a signal indicative of a phase difference between the first and last clock signals; and

a control signal generator configured to receive the signal indicative of the phase difference between the first and last clock signals and generate a control signal to adjust the delay of the plurality of delay elements such that the first, intermediate and third delay element have a predetermined phase relationship; and

an array of memory cells, the array of memory cells coupled to receive the intermediate and last clock signals.

20. The memory device of claim 19 further comprising:

a delay locked loop configured to receive the input clock signal and output the first clock signal, the delay locked loop configured to generate the first clock signal by delaying the input clock signal by a delay amount, the delay locked loop further configured to receive a feedback signal and adjust a delay of the delay line such that the first clock signal input to the multi-phase clock signal generator is in phase with a clock signal received by the array of memory cells.

21. The memory device of claim 20 wherein the feedback signal comprises the first clock signal coupled through an output model delay element having a delay amount substantially equal to an amount of delay between the input of the multi-phase clock signal generator and the array of memory cells.

22. The memory device of claim 20 wherein the feedback signal comprises the first clock signal output from the multi-phase clock signal generator coupled through an output model delay element having a delay amount substantially equal to an amount of delay between the output of the multi-phase clock signal generator and the array of memory cells.

23. A method for generating a plurality of periodic signals including a first clock signal, an intermediate clock signal having a first phase relationship with the first clock signal, and final clock signal having a second phase relationship with the first clock signal, the method comprising:

delaying the first signal a first delay amount to generate the intermediate clock signal;

delaying the intermediate signal a second delay amount to generate the final signal;

enabling a phase detector using the intermediate signal;

measuring a phase difference between the first and final signals while the phase detector is enabled; and

adjusting the first and second delay amounts based on the phase difference.

24. The method according to claim 23 further comprising inverting the intermediate signal prior to enabling the phase detector using the intermediate signal.

25. The method according to claim 24 further comprising delaying the first and final signals a compensation delay amount prior to measuring the phase difference between the first and final signals.

26. The method according to claim 25 wherein the compensation delay amount delays the first and last signals such that rising edges of the first and last signals occur while the phase detector is enabled.

27. The method according to claim 25 further comprising changing the compensation delay amount at least in part based on a frequency of the first clock signal.

28. The method according to claim 25 wherein the act of measuring the phase difference comprises generating a first difference signal corresponding to a length of time the inverted intermediate signal and the delayed first signal have a same logic level and generating a second difference signal corresponding to a length of time the inverted intermediate signal and the delayed final signal have the same logic level.

29. The method according to claim 28 wherein the act of adjusting the first and second delay amounts comprises adjusting the first and second delay amounts to minimize a difference between the first and second difference signals.

30. The method according to claim 29 wherein the act of adjusting the first and second delay amounts comprises generating a course control signal and a fine control signal.

31. The method according to claim 25 wherein the act of measuring the phase difference comprises generating a first difference signal having a pulse from a rising edge of the inverted intermediate signal to a falling edge of the first signal and a second difference signal having a pulse from a rising edge of the inverted intermediate signal to a falling edge of the final signal.

32. The method according to claim 23 wherein the first phase relationship comprises 180 degrees and the second phase relationship comprises 360 degrees.

33. The method according to claim 23 further comprising coupling the first, intermediate, and final signals to a memory array.

34. The method according to claim 23 wherein the first and second delay amounts are adjusted to minimize the phase difference between the first and last signals and to alter the phase difference between the intermediate and last signals in a single adjustment.

35. The method according to claim 23 further comprising using the intermediate signal as a guide to measure the phase difference between the first and last signals.