INJECTION-LOCKED CLOCK MULTIPLIER

• US 20100085123A1
• Filed: 10/09/2009
• Published: 04/08/2010
• Est. Priority Date: 04/22/2008
• Status: Abandoned Application

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Frans, Yohan U., Lee, Hae-Chang, Leibowitz, Brian S., Kim, Jaeha
• Application Number:
  US12/577,027
• Publication Number:
  US 20100085123A1
• Time in Patent Office: Days
• US Class Current: 331/47
• CPC Class Codes: H03L 7/083 the reference signal being additionally directly applied to the generator
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence

Abstract

Embodiments of a clock circuit are described. This clock circuit includes an oscillator, which includes a resonance circuit having a resonance frequency, that outputs a first clock signal having a first frequency. Furthermore, a digital controller is coupled to the oscillator. This digital controller modifies the resonance frequency of the oscillator during a first mode of operation of the clock circuit, and the modifying is ceased during a second mode of operation of the clock circuit. In addition, on injection circuit is coupled to the oscillator. This injection circuit provides a second clock signal having a second frequency to the oscillator. Note that the second clock signal injection locks a phase and/or the first frequency of the first clock signal. Also note that a ratio of the first frequency to the second frequency is greater than or equal to one.

Claims

1. A clock circuit, comprising:

an oscillator, including a resonance circuit, having a resonance frequency, to output a first clock signal having a first frequency;

a digital controller, coupled to the oscillator, to modify the resonance frequency during a first mode of operation of the clock circuit and to cease the modifying during a second mode of operation of the clock circuit; and

an injection circuit, coupled to the oscillator, to provide a second clock signal having a second frequency to the oscillator to injection lock a phase and the first frequency of the first clock signal, wherein a ratio of the first frequency to the second frequency is greater than or equal to one.

2. The clock circuit of claim 1, wherein the ratio is an integer.

3. The clock circuit of claim 1, wherein the second clock signal includes pulses.

4. The clock circuit of claim 1, wherein the digital controller is to adjust the resonance frequency of the oscillator.

5. The clock circuit of claim 4, wherein the digital controller is to determine a frequency difference between a first signal corresponding to the first clock signal and a second signal corresponding to the second clock signal, and wherein the adjustment is based on the frequency difference.

6. The clock circuit of claim 4, wherein the digital controller is to determine a phase difference between a first signal corresponding to the first clock signal and a second signal corresponding to the second clock signal, and wherein the adjustment is based on the phase difference.

7. The clock circuit of claim 6, wherein the phase difference includes a static phase offset.

8. The clock circuit of claim 1, wherein the injection circuit is capacitively coupled to the oscillator.

9. The clock circuit of claim 8, wherein the capacitive coupling includes a capacitive divider.

10. The clock circuit of claim 1, further comprising an output buffer coupled to the oscillator.

11. The clock circuit of claim 1, wherein the oscillator is coupled to a filter.

12. The clock circuit of claim 11, wherein the filter includes a resonant-clock-distribution network.

13. The clock circuit of claim 1, further comprising a regeneration circuit coupled to the resonance circuit in the oscillator, wherein the regeneration circuit is to restore energy in the oscillator.

14. The clock circuit of claim 13, wherein the regeneration circuit is to have a negative transconductance.

15. The clock circuit of claim 13, wherein the clock circuit is to operate in a third mode of operation;

wherein during the third mode of operation the regeneration circuit, the digital controller, and the injection circuit are to be disabled; and

wherein when transitioning from the third mode of operation to the second mode of operation, the digital controller is enabled and is to set the resonance frequency based on a stored value, then the injection circuit and the regeneration circuit are enabled, and the injection circuit is to provide the second clock signal.

16. The clock circuit of claim 1, wherein the resonance circuit includes an inductor and a capacitor, and wherein the digital controller is to modify a capacitance of the capacitor.

17. The clock circuit of claim 1, wherein the injection circuit is an open-loop controller.

18. The clock circuit of claim 1, wherein the injection circuit is to receive a third clock signal;

wherein the second clock signal is based on the third clock signal; and

wherein the second clock signal is different than the third clock signal.

19. The clock circuit of claim 1, wherein the oscillator is to output a fourth clock signal having the first frequency;

wherein the fourth clock signal is out of phase with respect to the first clock signal;

wherein the injection circuit is to provide a fifth clock signal having the second frequency; and

wherein the fifth clock signal is out of phase with respect to the second clock signal.

20. A clock circuit, comprising:

an oscillator, including a resonance circuit having a resonance frequency, to output a first clock signal having a first frequency;

a digital controller, coupled, to the oscillator, to modify the resonance frequency during a first mode of operation of the clock circuit and to cease the modifying during a second mode of operation of the clock circuit; and

an injection circuit, coupled to the oscillator, including a pulse circuit to provide a second clock signal having a second frequency to the oscillator to injection lock a phase and the first frequency of the first clock signal, wherein the second clock signal includes pulses having a time spacing corresponding to the second frequency; and

wherein a ratio of the first frequency to the second frequency is greater than or equal to one.

21. An integrated circuit, comprising a clock circuit, wherein the clock circuit includes:

an oscillator, including a resonance circuit having a resonance frequency, to output a first clock signal having a first frequency;

a digital controller, coupled to the oscillator, to modify the resonance frequency during a first mode of operation of the clock circuit and to cease the modifying during a second mode of operation of the clock circuit; and

an injection circuit, coupled to the oscillator, to provide a second clock signal having a second frequency to the oscillator to injection lock a phase and the first frequency of the first clock signal, wherein a ratio of the first frequency to the second frequency is greater than or equal to one.

22. A clock circuit, comprising:

an oscillator, including a resonance circuit having a resonance frequency, to output a first clock signal having a first frequency;

a digital controller, coupled to the oscillator, to modify the resonance frequency during a first mode of operation of the clock circuit and to cease the modifying during a second mode of operation of the clock circuit; and

means for providing a second clock signal having a second frequency to the oscillator to injection lock a phase and the first frequency of the first clock signal, wherein a ratio of the first frequency to the second frequency is greater than or equal to one.

23. A method for generating a clock signal, comprising:

driving a resonance circuit in an oscillator, which outputs a first clock signal having a first frequency, with a regeneration circuit, wherein the regeneration circuit is to restore energy in the oscillator;

modifying a resonance frequency of the resonance circuit using a digital controller during a first mode of operation of the clock circuit, wherein the modifying is ceased during a second mode of operation of the clock circuit, and wherein after the modifying the first frequency is within a pre-determined range of frequencies around a target frequency; and

injection locking the first frequency of the oscillator to the target frequency by coupling a second clock signal having a second frequency to the oscillator, wherein a ratio of the first frequency to the second frequency is greater than or equal to one.