ORGANIC LIGHT EMITTING DIODE DISPLAY

• US 20100085282A1
• Filed: 10/07/2009
• Published: 04/08/2010
• Est. Priority Date: 10/07/2008
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Woo, Kyoungdon, Lee, Jaedo, Hong, Youngjun, Yu, Sangho
• Granted Patent: US 8,446,345 B2
• Time in Patent Office: Days
• US Class Current: 345/76
• CPC Class Codes: G09G 2300/0852 being a dynamic memory with more than one capacitor
• CPC Class Codes: G09G 2310/0254 Control of polarity reversal in general, other than for liquid crystal displays
• CPC Class Codes: G09G 2320/0295 by monitoring each display pixel
• CPC Class Codes: G09G 2320/043 Preventing or counteracting the effects of ageing
• CPC Class Codes: G09G 3/3233 with pixel circuitry controlling the current through the light-emitting element
• CPC Class Codes: G09G 3/3275 Details of drivers for data electrodes

Abstract

An organic light emitting diode (OLED) display is disclosed. The OLED display includes a display panel including a plurality of pairs of data lines, a plurality of gate line groups crossing the pairs of data lines, and a plurality of pixels each having a drive thin film transistor (TFT) and an organic light emitting diode at each of crossings of the pairs of data lines and the gate line groups, a timing controller generating a non-overlap signal, and a sample and hold block that removes an overlap period between adjacently generated first holding clocks using the non-overlap signal to generate second holding clocks that do not overlap each other, applies sampled threshold voltages of the drive TFTs of the pixels to an output node in response to the second holding clocks, and discharges the output node in the overlap period in response to the non-overlap signal.

Claims

1. An organic light emitting diode (OLED) display comprising:

a display panel including a plurality of pairs of data lines, a plurality of gate line groups crossing the plurality of pairs of data lines, and a plurality of pixels each having two drive thin film transistors and an organic light emitting diode;

a timing controller that generates a non-overlap signal; and

a sample and hold block that removes an overlap period between adjacently generated first holding clocks using the non-overlap signal to generate second holding clocks that do not overlap each other, applies sampled threshold voltages of the drive thin film transistors of the pixels to an output node in response to the second holding clocks, and discharges the output node in the overlap period in response to the non-overlap signal.

2. The OLED display of claim 1, further comprising:

an analog-to-digital converter (ADC) that converts the threshold voltages of the drive thin film transistors input through the output node into digital threshold voltages; and

a memory that stores the digital threshold voltages and location information of the digital threshold voltages;

wherein the timing controller controls display data using the digital threshold voltages corresponding to location information of the display data received from the outside based on information stored in the memory.

3. The OLED display of claim 1, wherein the sample and hold block includes:

a sampling switch array including a plurality of sampling switches that are switched on in response to a sampling clock, the sampling switch array sampling the threshold voltages of the drive thin film transistors using the sampling switches;

a shift register array including a plurality of cascade-connected stages, the shift register array generating the first holding clocks using the plurality of cascade-connected stages;

an overlap prevention unit that performs an AND operation on the non-overlap signal and the first holding clocks to generate the second holding clocks;

a holding switch array including a plurality of holding switches that are switched on in response to the second holding clocks, the holding switch array sequentially outputting the sampled threshold voltages of the drive thin film transistors to the output node using the holding switches; and

a discharging unit that discharges charges remaining in the output node in the overlap period in response to the non-overlap signal.

4. The OLED display of claim 3, wherein the overlap prevention unit includes a plurality of AND elements each connected between the shift register array and the holding switch array.

5. The OLED display of claim 3, wherein the discharging unit includes:

a phase inversion unit that inverts a phase of the non-overlap signal; and

a discharge switch that is connected between the common output node and a ground level voltage source and is controlled by an output of the phase inversion unit.

6. The OLED display of claim 3, wherein the non-overlap signal has a first logic level different from a level of the first holding clocks in a non-overlap period and has a second logic level identical with the level of the first holding clocks in the non-overlap period.

7. The OLED display of claim 6, wherein the discharge switch is turned on in response to the first logic level of the non-overlap signal.

8. The OLED display of claim 1, wherein each pixel includes one pair of data lines and one gate line group.

9. The OLED display of claim 1, wherein each gate line group includes four gate lines.

10. The OLED display of claim 1, wherein each pixel further includes four switch thin film transistors.

11. The OLED display of claim 3, wherein two drive thin film transistors connected in parallel between a cathode electrode of the organic light emitting diode and a low potential driving voltages source.

12. The OLED display of claim 11, wherein the sampling switch array simultaneously samples threshold voltages of one drive thin film transistors on 1 horizontal line during 1 frame period and sequentially performs a sampling operation during a first period including n frame periods, wherein n is a vertical resolution,

wherein the sampling switch array simultaneously samples threshold voltages of the other drive thin film transistors on one horizontal line during one frame period and sequentially performs a sampling operation during a second period including n frame periods following the first period.

13. The OLED display of claim 12, wherein each pair of the plurality of pairs of data lines includes a first data line for driving the one drive thin film transistor and a second data line for driving the other drive thin film transistor,

wherein the sampling switches of the sampling switch array are alternately connected to the first data lines and the second data lines each for n frame periods.