CHIP PACKAGE STRUCTURE WITH SHIELDING COVER

• US 20100085719A1
• Filed: 07/29/2009
• Published: 04/08/2010
• Est. Priority Date: 10/07/2008
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: Lu, Hsin-Chieh, Chou, Chin-Feng
• Granted Patent: US 8,102,669 B2
• Time in Patent Office: Days
• US Class Current: 361/782
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 2924/19105 in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H05K 5/0091 Housing specially adapted for small components for resistors H01C; for capacitors H01G; for integrated circuits H01L23/00
• CPC Class Codes: H05K 9/0026 integrally formed from metal sheet

Abstract

A chip package structure with a shielding cover includes a substrate, a chip, a pair of first passive components, a pair of second passive components, and a shielding cover. The chip, the pair of first passive components, the pair of second passive components, and the shielding cover are disposed on the substrate. The chip is electrically connected to the substrate. The shielding cover covers the chip and has leads connected to the substrate. The leads include a first lead and a second lead. The first lead connected to a portion of the substrate is located between the pair of first passive components and arranged along a first axis with the pair of first passive components. The second lead connected to a portion of the substrate is located between the pair of second passive components and arranged along a second axis with the pair of second passive components.

Claims

1. A chip package structure with a shielding cover, comprising:

a substrate;

a chip, disposed on and electrically connected to the substrate;

a pair of first passive components, disposed on the substrate;

a pair of second passive components, disposed on the substrate; and

a shielding cover, disposed on the substrate and covering the chip, the shielding cover having a plurality of leads connected to the substrate, the leads including a first lead and a second lead, wherein the first lead connected to a portion of the substrate is located between the pair of first passive components and arranged along a first axis with the pair of first passive components, and the second lead connected to a portion of the substrate is located between the pair of second passive components and arranged along a second axis with the pair of second passive components.

2. The chip package structure with the shielding cover as claimed in claim 1, wherein the pair of first passive components, the pair of second passive components, the first lead, and the second lead are electrically connected to the substrate through a conductive material.

3. The chip package structure with the shielding cover as claimed in claim 2, wherein the conductive material comprises conductive paste or solder paste.

4. The chip package structure with the shielding cover as claimed in claim 1, wherein the substrate has a rectangular shape.

5. The chip package structure with the shielding cover as claimed in claim 4, wherein the first lead and the pair of first passive components are arranged along the first axis, the second lead and the pair of second passive components are arranged along the second axis, and the first axis is substantially perpendicular to the second axis.

6. The chip package structure with the shielding cover as claimed in claim 5, the substrate further comprising a pair of third passive components and a pair of fourth passive components, the leads further comprising a third lead and a fourth lead, the pair of third passive components and the pair of first passive components being respectively located at two opposite diagonal corners of the substrate, the pair of fourth passive components and the pair of second passive components being respectively located at the other two opposite diagonal corners of the substrate, wherein the third lead connected to a portion of the substrate is located between the pair of third passive components and arranged, together with the pair of third passive components, along an axis substantially parallel to the first axis, the fourth lead connected to a portion of the substrate is located between the pair of fourth passive components and arranged, together with the pair of fourth passive components, along an axis substantially parallel to the second axis.

7. The chip package structure with the shielding cover as claimed in claim 6, wherein the pair of first passive components, the pair of second passive components, the pair of third passive components, the pair of fourth passive components, the first lead, the second lead, the third lead, and the fourth lead are electrically connected to the substrate through a conductive material.

8. The chip package structure with the shielding cover as claimed in claim 7, wherein the conductive material comprises conductive paste or solder paste.

9. The chip package structure with the shielding cover as claimed in claim 1, the substrate further comprising a pair of third passive components and a pair of fourth passive components, the leads further comprising a third lead and a fourth lead, the pair of third passive components and the pair of first passive components being respectively located at two opposite sides with respect to the center of gravity of the substrate, the pair of fourth passive components and the pair of second passive components being respectively located at the other two opposite sides with respect to the center of gravity of the substrate, wherein the third lead connected to a portion of the substrate is located between the pair of third passive components and arranged, together with the pair of third passive components, along an axis substantially parallel to the first axis, the fourth lead connected to a portion of the substrate is located between the pair of fourth passive components and arranged, together with the pair of fourth passive components, along an axis substantially parallel to the second axis.

10. The chip package structure with the shielding cover as claimed in claim 1, wherein the shielding cover comprises a top wall and a side wall perpendicularly connected to edges of the top wall.

11. The chip package structure with the shielding cover as claimed in claim 10, each of the leads comprising a leg and a base, wherein an end of the leg is connected to an edge of the top wall, the other end of the leg is connected to an end of the base, a surface of the base is connected to a portion of the substrate, and an extending direction of the base is substantially parallel to an extending direction of the top wall.