HYBRID SHALLOW TRENCH ISOLATION FOR HIGH-K METAL GATE DEVICE IMPROVEMENT

• US 20100087043A1
• Filed: 12/08/2008
• Published: 04/08/2010
• Est. Priority Date: 10/06/2008
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: THEI, Kong-Beng, CHENG, Chung Long, CHUANG, Harry
• Granted Patent: US 8,367,515 B2
• Time in Patent Office: Days
• US Class Current: 438/424
• CPC Class Codes: H01L 21/76229 Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/105 including field-effect components

Abstract

A method for fabricating a semiconductor device with improved performance is disclosed. The method comprises providing a substrate including a first region and a second region; forming at least one isolation region having a first aspect ratio in the first region and at least one isolation region having a second aspect ratio in the second region; performing a high aspect ratio deposition process to form a first layer over the first and second regions of the substrate; removing the first layer from the second region; and performing a high density plasma deposition process to form a second layer over the first and second regions of the substrate.

Claims

1. A method for fabricating an integrated circuit, the method comprising:

providing a substrate including a first region and a second region;

forming at least one isolation region having a first aspect ratio in the first region and at least one isolation region having a second aspect ratio in the second region;

performing a high aspect ratio deposition process to form a first layer over the first and second regions of the substrate;

removing the first layer from the second region; and

performing a high density plasma deposition process to form a second layer over the first and second regions of the substrate.

2. The method of claim 1 wherein the first region comprises a memory cell area and the second region comprises a logic area.

3. The method of claim 1 wherein the first layer and the second layer comprises a thickness ranging from approximately 5,000 Å

to 10,000 Å

.

4. The method of claim 1 wherein the first aspect ratio is greater than the second aspect ratio.

5. The method of claim 1 wherein the first layer and the second layer comprises an oxide.

6. The method of claim 1 further comprising:

annealing the first layer over the first and second regions of the substrate; and

performing a chemical mechanical planarization on the first and second layers over the first and second regions.

7. The method of claim 6 wherein annealing the first layer comprises a temperature ranging from approximately 1,000°

C. to 1,200°

C. for a time period ranging from approximately 10 minutes to 5 hours.

8. The method of claim 1 further comprising:

forming a first liner layer over the first and second isolation regions prior to forming a first layer; and

forming a second liner layer over the second isolation region prior to forming the second layer.

9. The method of claim 8 wherein the first liner layer and the second liner layer comprises a thickness ranging from approximately 30 Å

to 100 Å

.

10. The method of claim 1 wherein removing the first layer from the second region comprises forming a masking layer over the first region and etching the first layer in the second region.

11. The method of claim 1 wherein the at least one isolation region having the first aspect ratio and the at least one isolation region having the second aspect ratio comprises a shallow trench isolation.

12. A method for fabricating an integrated circuit, the method comprising:

providing a substrate;

forming a first set of isolation regions and a second set of isolation regions having different aspect ratios on the substrate;

filling the first set of isolation regions by a first deposition process including a high aspect ratio deposition process; and

filling the second set of isolation regions by a second deposition process including a high density plasma deposition process.

13. The method of claim 12 wherein forming the first set of isolation regions and the second set of isolation regions comprises etching the substrate to form at least one trench.

14. The method of claim 12 wherein filling the first set of isolation regions and the second set of isolation regions comprises filling the regions to a thickness ranging from approximately 5,000 Å

to 10,000 Å

.

15. The method of claim 12 wherein forming the first set of isolation regions and the second set of isolation regions having different aspect ratios comprises forming the first set of isolation regions with an aspect ratio greater than the second set of isolation regions.

16. The method of claim 12 further comprising:

forming a first liner layer over the first set of isolation regions prior to filling the first set of isolation regions by the first deposition process; and

forming a second liner layer over the first set of isolation regions prior to filling the second set of isolation regions by the second deposition process.

17. The method of claim 16 wherein the first liner layer and the second liner layer comprises a thickness ranging from approximately 30 Å

to 100 Å

.

18. The method of claim 12 further comprising:

performing an annealing process after filling the first set of isolation regions; and

performing a chemical mechanical planarization after filling the first set of isolation regions and the second set of isolation regions.

19. The method of claim 18 wherein the annealing process comprises a temperature ranging from approximately 1,000°

C. to 1,200°

C. for a time period ranging from approximately 10 minutes to 5 hours.

20. A method for fabricating an integrated circuit, the method comprising:

providing a substrate;

forming a first trench and a second trench on the substrate;

filling the first trench with a first deposition process including a high aspect ratio process oxide; and

filling the second trench with a second deposition process including a high density plasma oxide.