SOLID STATE STORAGE SYSTEM USING GLOBAL WEAR LEVELING AND METHOD OF CONTROLLING THE SOLID STATE STORAGE SYSTEM

• US 20100088461A1
• Filed: 12/29/2008
• Published: 04/08/2010
• Est. Priority Date: 10/02/2008
• Status: Abandoned Application

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: YANG, Wun Mo, KWAK, Jeong Soon, KIM, Kyeong Rho
• Application Number:
  US12/344,702
• Publication Number:
  US 20100088461A1
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 2212/7211 Wear leveling

Abstract

A solid state storage system is disclosed including a memory area having a plurality of chips. The solid state storage system includes a micro controller unit (MCU) configured to utilize the number of deletions for logical blocks corresponding to logical block addresses when performing wear leveling on the memory area. The allocation of the logical block addresses can be performed using an interleaving process and a multi-plane method. The solid state storage system performs global wear leveling by which the lifespan of the cells of the chips can be uniformly managed.

Claims

1. A solid state storage system, comprising:

a memory area including a plurality of chips; and

a micro controller unit (MCU) using a number of times logical blocks that correspond to selected logical block addresses are deleted when wear leveling is performed on the memory area.

10. A solid state storage system, comprising:

a memory area including a plurality of chips; and

a micro controller unit (MCU) allocating continuous logical block addresses to different chips of the plurality of chips, respectively, and performing wear leveling on the memory area,

wherein, when a logical block of a chip generates a threshold value or more for a number of deletions, the MCU allocates the logical block to physical blocks of the plurality of chips other than the chip including the logical block to support global wear leveling.

2. The solid state storage system of claim 11

wherein according to a write request, the MCU increases the number of times the logical block that corresponds to a selected logical block address is deleted, determines a threshold value for the number of deletions of the logical block, and remaps the logical block address.

3. The solid state storage system of claim 2,

wherein the MCU traces the logical block having a predetermined number of deletions and a newly mapped free block.

4. The solid state storage system of claim 3,

wherein the solid state storage system uses a file system method that manages data in a cluster unit, and

the MCU groups the logical block addresses by a predetermined number corresponding to the cluster unit.

5. The solid state storage system of claim 4,

wherein the MCU traces a free block having a least number of deletions among free blocks corresponding to the grouped logical block addresses that form the cluster unit including the selected logical block address in the chips that do not include the logical block.

6. The solid state storage system of claim 5,

wherein the traced free block having the least number of deletions and the logical block are mapped.

7. The solid state storage system of claim 4,

wherein the MCU traces free blocks corresponding to the logical block addresses that form the cluster unit including the selected logical block address with respect to a chip subsequent to the chip including the logical block.

8. The solid state storage system of claim 7,

wherein the subsequent chip is determined according to a round robin method.

9. The solid state storage system of claim 7,

wherein the MCU continuously traces free blocks newly mapped to all of the chips other than the logical block and performs new mapping on predetermined logical blocks of all of the chips.

11. The solid state storage system of claim 10,

wherein according to a write request, the MCU increases a number of times a selected logical block address is deleted, determines the threshold value for the number of deletions of the logical block, and remaps the logical block.

12. The solid state storage system of claim 11,

wherein the MCU traces the logical block having a predetermined number of deletions and a newly mapped free block.

13. The solid state storage system of claim 12,

wherein the solid state storage system uses a file system method that manages data in a cluster unit, and

the MCU groups the logical block addresses by a predetermined number corresponding to the cluster unit.

14. The solid state storage system of claim 13,

wherein the MCU traces a free block having a least number of deletions among free blocks corresponding to the grouped logical block addresses that form the cluster unit including the selected logical block address in the chips that do not include the logical block.

15. The solid state storage system of claim 14,

wherein the traced free block having the least number of deletions and the logical block are mapped.

16. The solid state storage system of claim 13,

wherein the MCU traces free blocks corresponding to the logical block addresses that form the cluster unit including the selected logical block address with respect to a chip subsequent to the chip including the logical block.

17. The solid state storage system of claim 16,

wherein the subsequent chip is determined according to a round robin method.

18. The solid state storage system of claim 16,

wherein the MCU continuously traces free blocks newly mapped to all of the chips other than the logical block and performs new mapping on predetermined logical blocks of all of the chips.

19. The solid state storage system of claim 10,

wherein each of the plurality of chips includes a plurality of planes and each of the plurality of planes includes a plurality of blocks, and

the MCU groups the plurality of blocks included in different planes of the plurality of planes in the same chip and allocates the logical block addresses to the groups of blocks.

20. The solid state storage system of claim 19,

wherein the logical block addresses define a virtual page unit, and

a read/write operation is performed in the virtual page unit.

21. A method of controlling a solid state storage system using a file system method that manages data in a cluster unit, comprising:

increasing a number of times a logical block designated by a selected logical block address is deleted when data for the selected logical block address is updated in response to a command from an external host;

determining whether the number of times the logical block address is deleted exceeds a threshold value for a number of deletions; and

mapping the logical block to free blocks of different chips when the number of times the logical block address is deleted exceeds the threshold value.

22. The method of claim 21, wherein the mapping of the logical block to the free blocks of the different chips includes:

tracing a free block, in the different chips that do not include the logical block, having a least number of deletions among free blocks corresponding to logical block address groups that form a cluster that includes the logical block address;

mapping the free block corresponding to the logical block and the traced new free block; and

resetting the number of times the logical block is deleted after the free blocks are mapped.

23. The method of claim 21, wherein the mapping of the logical block to the free blocks of the different chips includes:

tracing a replaced free block of a subsequent chip determined by a round robin method with respect to all chips that include the logical block;

mapping a continuously selected logical block in each chip and the traced free block of the subsequent chip; and

resetting the number of times the logical block is deleted after the continuously selected logical blocks are remapped.

24. The method of claim 23, wherein the tracing of the replaced free block includes:

tracing a free block of a subsequent chip corresponding to the logical block address that forms the cluster unit including the selected logical block address and a free block of a subsequent chip mapped to the logical block corresponding to the traced free block.

25. The method of claim 21, further comprising:

when each of the different chips includes a plurality of planes and each of the plurality of planes includes a plurality of blocks,

before the increasing of the number of times the logical block is deleted,

generating logical block addresses in a virtual page unit by grouping the plurality of blocks included in different planes of the plurality of planes in the same chip and mapping the logical block addresses to physical blocks of the different chips.