SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND IC CARD USING THE SAME

• US 20100088534A1
• Filed: 10/02/2009
• Published: 04/08/2010
• Est. Priority Date: 10/02/2008
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Yonea, Nobuaki, WATANABE, Kazuki
• Granted Patent: US 8,301,915 B2
• Time in Patent Office: Days
• US Class Current: 713/340
• CPC Class Codes: G06K 19/0701 at least one of the integrated circuit chips comprising an arrangement for power management
• CPC Class Codes: G06K 19/0723 the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs
• CPC Class Codes: G06K 19/07769 the further communication means being a galvanic interface, e.g. hybrid or mixed smart cards having a contact and a non-contact interface

Abstract

The present invention enables a power-supply voltage terminal and an internal circuit to be isolated from each other in a noncontact operation without largely increasing a chip area in a semiconductor integrated circuit device for an IC card. A semiconductor integrated circuit device comprises: a first power supply circuit for rectifying and smoothing an AC signal supplied from an antenna to an antenna terminal, thereby obtaining a DC voltage in a first power-supply line; a second power supply circuit comprising a voltage control circuit for controlling gate terminal voltage of a first MOS transistor disposed between a power supply terminal to which power is input from the outside and the first power supply line; a substrate potential control circuit for forming source voltage of the first MOS transistor as a substrate voltage; and a second MOS transistor which makes substrate voltage and gate voltage of the first MOS transistor conductive in the case of using the voltage generated by the first power supply circuit as a power supply, and which makes the substrate voltage and the gate voltage nonconductive in the case of using a power supply from an external terminal.

Claims

1. A semiconductor integrated circuit device comprising:

an antenna terminal coupled to an antenna;

a first power supply circuit for rectifying and smoothing an AC signal supplied from the antenna to the antenna terminal, thereby obtaining a DC voltage in a first power supply line;

a power supply terminal and a ground terminal to which power is supplied from the outside;

a second power supply circuit comprising a first MOS transistor disposed between the power supply terminal and the first power supply line and a voltage control circuit for controlling a voltage of a gate terminal of the first MOS transistor; and

a substrate potential control circuit for controlling substrate voltage of the first MOS transistor,

wherein in the case of using the voltage generated by the first power supply circuit as a power supply, the first MOS transistor is interrupted, thereby isolating the power supply terminal and the first power supply line from each other, and

wherein in the case of using a power supply from an external terminal, the power supply control circuit controls the first MOS transistor to suppress voltages supplied from the power supply terminal and the ground terminal to a predetermined voltage and outputs the resultant voltage to the first power supply line.

2. The semiconductor integrated circuit device according to claim 1, further comprising a second MOS transistor which makes substrate voltage and gate voltage of the first MOS transistor conductive in the case of using the voltage generated by the first power supply circuit as a power supply, and which makes the substrate voltage and the gate voltage nonconductive in the case of using a power supply from an external terminal.

3. The semiconductor integrated circuit device according to claim 2, wherein the substrate potential control circuit outputs the voltage of the first power supply line as the substrate voltage in a state where the first MOS transistor is interrupted, and outputs the voltage of the first power supply terminal as the substrate voltage in a state where the first MOS transistor is not interrupted.

4. The semiconductor integrated circuit device according to claim 3,

wherein the substrate potential control circuit comprises:

a third MOS transistor disposed between the output terminal of the substrate voltage and the power supply voltage;

a fourth MOS transistor disposed between the output terminal of the substrate voltage and the first power supply line; and

a gate voltage control circuit for controlling a gate terminal voltage of the third and fourth MOS transistors, and

wherein the gate voltage control circuit controls the substrate voltage of the first MOS transistor to be the same potential as the potential of the source terminal of the first MOS transistor by turning on the third MOS transistor when the potential of the power supply terminal is higher than that of the first power supply line, and turning on the fourth MOS transistor when the potential of the power supply terminal is lower than the potential of the first power supply line.

5. The semiconductor integrated circuit device according to claim 4,

wherein the third and fourth MOS transistors are P-channel-type MOS transistors in each of which a substrate has the same potential as that of an output terminal of the substrate voltage, and

wherein the gate voltage control circuit comprises a wire for coupling the gate of the third MOS transistor to the first power supply line, and a wire for coupling the gate of the fourth MOS transistor to the power supply terminal.

6. The semiconductor integrated circuit device according to claim 1, further comprising a pull-down circuit between the power supply terminal and the ground terminal,

wherein the pull-down circuit decreases a resistance value between the power supply terminal and the ground terminal on the basis of detection by the detection circuit, of formation of a power supply based on the AC signal.

7. The semiconductor integrated circuit device according to claim 1, wherein the detection circuit operates on voltage input to the substrate terminal of the first MOS transistor as a power supply voltage.

8. The semiconductor integrated circuit device according to claim 1, further comprising an internal circuit which operates on voltage supplied to the first power supply line as a power supply voltage.

9. An IC card comprising:

a coil forming an antenna;

a plurality of metal terminals forming a coupling terminal; and

the semiconductor integrated circuit device according to claim 1,

wherein an antenna terminal of the semiconductor integrated circuit device is coupled to the coil, and

wherein a power supply terminal and a ground terminal of the semiconductor integrated circuit device are coupled to a predetermined metal terminal.

10. A semiconductor integrated circuit device comprising:

a first power supply circuit for rectifying and smoothing an AC signal supplied from an antenna to an antenna terminal, thereby obtaining a DC voltage in a first power supply line;

a second power supply circuit comprising a voltage control circuit for controlling gate terminal voltage of a first MOS transistor disposed between a power supply terminal to which power is input from the outside and the first power supply line;

a substrate potential control circuit for forming source voltage of the first MOS transistor as a substrate voltage; and

a second MOS transistor which makes substrate voltage and gate voltage of the first MOS transistor conductive in the case of using the voltage generated by the first power supply circuit as a power supply, and which makes the substrate voltage and the gate voltage nonconductive in the case of using a power supply from an external terminal.

11. The semiconductor integrated circuit device according to claim 10, wherein the substrate potential control circuit outputs the voltage of the first power supply line as the substrate voltage in a state where the first MOS transistor is interrupted, and outputs the voltage of the first power supply terminal as the substrate voltage in a state where the first MOS transistor is not interrupted.

12. The semiconductor integrated circuit device according to claim 11,

wherein the substrate potential control circuit comprises:

a third MOS transistor disposed between the output terminal of the substrate voltage and the power supply voltage;

a fourth MOS transistor disposed between the output terminal of the substrate voltage and the first power supply line; and

a gate voltage control circuit for controlling a gate terminal voltage of the third and fourth MOS transistors, and

wherein the gate voltage control circuit controls the substrate voltage of the first MOS transistor to be the same potential as the potential of the source terminal of the first MOS transistor by turning on the third MOS transistor when the potential of the power supply terminal is higher than that of the first power supply line, and turning on the fourth MOS transistor when the potential of the power supply terminal is lower than the potential of the first power supply line.

13. The semiconductor integrated circuit device according to claim 12,

wherein the third and fourth MOS transistors are P-channel-type MOS transistors in each of which a substrate has the same potential as that of an output terminal of the substrate voltage, and

wherein the gate voltage control circuit comprises a wire for coupling the gate of the third MOS transistor to the first power supply line, and a wire for coupling the gate of the fourth MOS transistor to the power supply terminal.

14. An IC card comprising:

a coil forming an antenna;

a plurality of metal terminals forming a coupling terminal; and

the semiconductor integrated circuit device according to claim 10,

wherein an antenna terminal of the semiconductor integrated circuit device is coupled to the coil, and

wherein a power supply terminal and a ground terminal of the semiconductor integrated circuit device are coupled to a predetermined metal terminal.