METHOD AND SYSTEM FOR SELECTING TEST VECTORS IN STATISTICAL VOLUME DIAGNOSIS USING FAILED TEST DATA

• US 20100088560A1
• Filed: 10/03/2008
• Published: 04/08/2010
• Est. Priority Date: 10/03/2008
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Singh, Ratan Deep H., Chakravarthy, Sameer H., Swenton, Joseph Michael, Bartenstein, Thomas Webster, Bhabu, Shaleen
• Granted Patent: US 8,190,953 B2
• Time in Patent Office: Days
• US Class Current: 714/724
• CPC Class Codes: G01R 31/31718 Logistic aspects, e.g. binning, selection, sorting of devices under test, tester/handler interaction networks, Test management software, e.g. software for test statistics or test evaluation, yield analysis mechanical aspects G01R31/2808, G01R31/2851
• CPC Class Codes: G01R 31/318371 Methodologies therefor, e.g. algorithms, procedures

Abstract

A method and system for test vector selection in statistical volume diagnosis using failed test data is disclosed. A computer-implemented method receives failures representing defects detected by an integrated circuit testing apparatus from a plurality of integrated circuits. Each of the plurality of integrated circuits is tested with a set of test vectors generated by the integrated circuit testing apparatus, and each of the plurality of failures is associated with a failed test vector. Using a first ranking scheme, each of the failures is given a rank and the corresponding failed test vector in each of the plurality of integrated circuits is annotated with the rank. The annotated failed test vectors are grouped using a grouping scheme, and each of the groups is given a group rank. A first group of failed test vectors is selected based on the group rank and diagnostics is run on the first group of tailed test vectors.

Claims

1. A computer-implemented method, comprising:

receiving failures representing defects detected by an integrated circuit testing apparatus from a plurality of integrated circuits, wherein each of the plurality of integrated circuits is tested with a set of test vectors generated by the integrated circuit testing apparatus and each of said failures is associated with a failed test vector;

generating ranks for each of said failures using a first ranking scheme;

annotating said ranks to the failed test vector for each of said failures in each of the plurality of integrated circuits;

generating a plurality of groups by grouping the failed test vectors in each of the plurality of integrated circuits using a grouping scheme;

assigning a group rank to each of the plurality of groups using a second ranking scheme;

selecting a first group of failed test vectors from the plurality of groups in each of the plurality of integrated circuits using a selection criterion; and

running diagnostics on the first group of failed test vectors.

2. The computer-implemented method of claim 1, wherein the first ranking scheme is one of a pattern scheme, a pattern-flop scheme and a flop scheme.

3. The computer-implemented method of claim 1, wherein each of the plurality of groups is further grouped into one or more subgroups using a second grouping scheme.

4. The computer-implemented method of claim 3, wherein the second grouping scheme is different from said grouping scheme.

5. The computer-implemented method of claim 3, wherein the first group of failed test vectors includes the failed test vectors at the top of the one or more subgroups.

6. The computer-implemented method of claim 1, wherein the first group of failed test vectors includes the group of the plurality of groups with the highest group rank.

7. The computer-implemented method of claim 1, wherein the selection criterion uses the group ranks and a threshold value to select the first group of failed test vectors.

8. The computer-implemented method of claim 1, further comprising:

generating callout data after running diagnostics on the first group of failed test vectors; and

running trend analysis based on the callout data.

9. The computer-implemented method of claim 8, wherein the selection criterion employs a multi-pass selection process comprising:

selecting integrated circuits that have more than a predetermined number of groups; and

selecting the first group of failed test vectors only from the failed test vectors in the selected integrated circuits.

10. The computer-implemented method of claim 9, further comprising

running diagnostics on the first group of failed test vectors;

and

determining that the failed test vector represents a systematic defect if the failed test vector is diagnosed in at least one group in each of all the selected integrated circuits.

11. A computer-readable medium having stored thereon a plurality of instructions, said plurality of instructions when executed by a computer, cause said computer to perform:

receiving failures representing defects detected by an integrated circuit testing apparatus from a plurality of integrated circuits, wherein each of the plurality of integrated circuits is tested with a set of test vectors generated by the integrated circuit testing apparatus and each of said failures is associated with a failed test vector;

generating ranks for each of said failures using a first ranking scheme;

annotating said ranks to the failed test vector for each of said failures in each of the plurality of integrated circuits;

generating a plurality of groups by grouping the failed test vectors in each of the plurality of integrated circuits using a grouping scheme;

assigning a group rank to each of the plurality of groups using a second ranking scheme;

selecting a first group of failed test vectors from the plurality of groups in each of the plurality of integrated circuits using a selection criterion; and

running diagnostics on the first group of failed test vectors.

12. The computer-readable medium of claim 11, wherein the first ranking scheme is one of a pattern scheme, a pattern-flop scheme and a flop scheme.

13. The computer-readable medium of claim 11, wherein each of the plurality of groups is further grouped into one or more subgroups using a second grouping scheme.

14. The computer-readable medium of claim 13, wherein the second grouping scheme is different from said grouping scheme.

15. The computer-readable medium of claim 13, wherein the first group of failed test vectors includes the failed test vectors at the top of the one or more subgroups.

16. The computer-readable medium of claim 11, wherein the first group of failed test vectors includes the group of the plurality of groups with the highest group rank.

17. The computer-readable medium of claim 11, wherein the selection criterion uses the group ranks and a threshold value to select the first group of failed test vectors.

18. The computer-readable medium of claim 11 having stored thereon a plurality of instructions, said plurality of instructions when executed by a computer, cause said computer to further perform:

generating callout data after running diagnostics on the first group of failed test vectors; and

running trend analysis based on the callout data.

19. The computer-readable medium of claim 18, wherein the selection criterion employs a multi-pass selection process comprising:

selecting integrated circuits that have more than a predetermined number of groups; and

selecting the first group of failed test vectors only from the failed test vectors in the selected integrated circuits.

20. The computer-readable medium of claim 19 having stored thereon a plurality of instructions, said plurality of instructions when executed by a computer, cause said computer to further perform:

running diagnostics on the first group of failed test vectors; and

determining that the failed test vector represents a systematic defect if the failed test vector is diagnosed in at least one group in each of all the selected integrated circuits.

21. A diagnostic system for identifying yield limiters using a group of failed test vectors, comprising:

a buffer that stores failures representing defects detected by an integrated circuit testing apparatus from a plurality of integrated circuits, wherein each of the plurality of integrated circuits is tested with a set of test vectors generated by the integrated circuit testing apparatus and each of said failures is associated with a failed test vector;

a diagnostic engine comprising a processor and random access memory for running diagnostics on the group of failed test vectors selected from a plurality of groups in each of said plurality of integrated circuits using a selection criteria, wherein said plurality of groups are generated by;

generating ranks to each of said failures using a first ranking scheme;

annotating said ranks to the failed test vectors for each of said failures in each of the plurality of integrated circuits;

grouping the failed test vectors in each of said plurality of integrated circuits using a grouping scheme, and;

assigning a group rank to each of the plurality of groups using a second ranking scheme.

22. The diagnostic system of claim 21, wherein the first ranking scheme is one of a pattern scheme, a pattern-flop scheme and a flop scheme.

23. The diagnostic system of claim 21, wherein each of the plurality of groups is further grouped into one or more subgroups using a second grouping scheme.

24. The diagnostic system of claim 23, wherein the second grouping scheme is different from said grouping scheme.

25. The diagnostic system of claim 23, wherein the first group of failed test vectors includes the failed test vectors at the top of the one or more subgroups.

26. The diagnostic system of claim 21, wherein the first group of failed test vectors includes the group of the plurality of groups with the highest group rank.

27. The diagnostic system of claim 21, wherein the selection criterion uses the group ranks and a threshold value to select the first group of failed test vectors.

28. The diagnostic system of claim 21, wherein trend analysis is run based on callout data generated after running diagnostics on the first group of failed test vectors.

29. The diagnostic system of claim 28, wherein the selection criterion employs a multi-pass selection process comprising:

selecting integrated circuits that have more than a predetermined number of groups; and

selecting the first group of failed test vectors only from the failed test vectors in the selected integrated circuits.

30. The diagnostic system of claim 29, wherein a systematic defect is found if the failed test vector is diagnosed in at least one group in each of all the selected integrated circuits.