TRANSISTOR STRUCTURE HAVING A TRENCH DRAIN

• US 20100090269A1
• Filed: 10/09/2008
• Published: 04/15/2010
• Est. Priority Date: 10/09/2008
• Status: Active Grant

• Current Assignee: Xenogenic Development Limited Liability Company (Intellectual Ventures LLC)
• Original Assignee: HVVi Semiconductors Incorporated
• Inventors: Davies, Robert Bruce
• Granted Patent: US 7,847,350 B2
• Time in Patent Office: Days
• US Class Current: 257/328
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/0882 Disposition
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402

Abstract

A semiconductor device is formed having a trench adjacent to a current carrying region of the device. The trench is formed having a depth greater than the depth of a tub region of the device. Increasing the trench depth moves a region of higher field strength from the tub region to a region along the trench. The region along the trench does not have a junction and may withstand the higher field strength.

Claims

1. A semiconductor device comprising:

a first region of a first conductivity type having a first major surface;

a first trench formed having a first surface below the first major surface of the first region and a sidewall;

a second region of the first conductivity type formed in proximity to the first major surface of the first region where the second region has a higher doping concentration than the first region; and

a third region of the first conductivity type formed in proximity to the sidewall of the first trench where the third region has a higher doping concentration than the first region.

2. The semiconductor device as recited in claim 1 further comprising:

a fourth region of the first conductivity type; and

a fifth region of a second conductivity type where at least a portion of the fifth region is between the fourth region and the first region.

3. The semiconductor device as recited in claim 1 further comprising a gate overlying the portion of the fifth region between the fourth region and the first region where the first region is coupled to a first electrode of the device, where the fourth region is coupled to a second electrode of the device, and the gate is coupled to the third electrode of the device.

4. The semiconductor device as recited in claim 2 where the fourth region is formed within the fifth region.

5. The semiconductor device as recited in claim 2 where the fourth and fifth region are electrically shorted together.

6. The semiconductor device as recited in claim 2 where a depth of the first trench from the first major surface is greater than a depth of the fifth region from the first major surface.

7. The semiconductor device as recited in claim 1 further comprising a first conductive shield in the trench approximately parallel to the sidewall of the first trench where the first conductive shield terminates near the first surface of the first trench.

8. The semiconductor device as recited in claim 7 further comprising a second conductive shield overlying the first trench.

9. The semiconductor device as recited in claim 8 where the first conductive shield couples to the second shield and where the first and second shield couple to the second electrode of the device.

10. The semiconductor device as recited in claim 1 further comprising a second trench below the first trench.

11. A semiconductor device comprising:

a substrate of a first conductivity type;

a first layer of the first conductivity type overlying the substrate, the first layer having a first major surface;

a first region of a second conductivity type formed in the first layer;

a second region of the first conductivity type formed in the first region where a channel region comprises a portion of the second region between a sidewall of the first region and the first layer;

a first trench in the first layer where the depth of the trench is greater than a depth of the first region;

a pedestal comprising at least one dielectric layer; and

a gate adjacent to a sidewall of the pedestal where the control electrode overlies the portion of the second region between a side wall of the first region and the first layer.

12. The semiconductor device of claim 11 further comprising a third region of the first conductivity type in proximity to the first major surface and where a portion of the third region is adjacent to the channel region.

13. The semiconductor device of claim 12 further comprising a fourth region of the first conductivity type adjacent to a sidewall of the first trench.

14. The semiconductor device of claim 13 wherein a doping concentration of the third region is greater than a doping concentration of the fourth region.

15. The semiconductor device of claim 11 further comprising a first conductive shield in the first trench approximately parallel to a sidewall of the first trench where the first conductive shield has a length approximately the same as a length of the sidewall of the first trench.

16. The semiconductor device of claim 11 further comprising a second conductive shield where at least a portion of the second shield is in the pedestal.

17. The semiconductor device of claim 12 further comprising a second trench below the first trench.

18. The semiconductor device of claim 17 wherein the second trench is formed through the first layer and into the substrate.

19. A method to achieve planar breakdown in a drain region of a transistor, the method comprising:

forming a tub region that includes a channel region of the transistor to a first depth where the tub region is an opposite conductivity type as the drain region;

forming a trench in the drain region of the transistor to a second depth; and

forming a dielectric layer overlying the trench where the trench second depth is greater than the tub region the first depth to reduce a field strength in proximity to the tub region whereby a voltage breakdown of the transistor is increased.

20. The method as recited in claim 19 further comprising moving a region of maximum or nearly maximum field strength to a corner region of the trench substantially below a major surface of the transistor where the dielectric layer does not breakdown under the maximum or nearly maximum field strength.

21. The method as recited in claim 19 further comprising:

implanting dopant of a same type as the drain region in proximity to a surface of the drain region and in proximity to a channel of the transistor to support current flow out of the channel region and into the drain region; and

implanting dopant through a sidewall of the trench to support current flow in proximity to the trench adjacent to the sidewall of the trench.

22. The method as recited in claim 19 further comprising a process of etching the trench greater than two times the depth of the tub region.

23. The method as recited in claim 19 further comprising a process of providing field line edge termination for the transistor.