TRENCH MOSFET WITH SHORT CHANNEL FORMED BY PN DOUBLE EPITAXIAL LAYERS

• US 20100090270A1
• Filed: 10/10/2008
• Published: 04/15/2010
• Est. Priority Date: 10/10/2008
• Status: Abandoned Application

• Current Assignee: Force Mos Technology Co., Ltd.
• Original Assignee: Force Mos Technology Co., Ltd.
• Inventors: Hsieh, Fu-Yuan
• Application Number:
  US12/249,453
• Publication Number:
  US 20100090270A1
• Time in Patent Office: Days
• US Class Current: 257/328
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A power MOS device includes double epitaxial (P/N) structure is disclosed for reduction of channel length and better avalanche capability. In some embodiments, the power MOS device further includes an arsenic Ion implantation area underneath each rounded trench bottom to further enhance breakdown voltage and further reduce Rds, and the concentration of said arsenic doped area is higher than that of N-type epitaxial layer. As the gate contact trench could be easily etched over to penetrate the gate oxide, which will lead to a shortage of tungsten plug filled in gate contact trench to epitaixial layer, a terrace poly gate is designed in a preferred embodiment of present invention. By using this method, the gate contact trench is lifted to avoid the shortage problem.

Claims

1. A trench MOSFET comprising:

a substrate made of first type semiconductor;

an epitaxial layer made of the first type semiconductor over substrate and having a lower doping concentration than the substrate;

a plurality of body regions made of second type semiconductor over the first epitaxial layer as body regions of the trench MOSFET;

a plurality of source regions made of first type semiconductor over the body regions as source regions of the trench MOSFET and having a higher doping concentration than the epitaxial layer;

a plurality of narrow trench gates formed to reach the epitaxial layer through the source region and the body region;

at least a wide trench gate formed to reach the epitaxial layer through the body region;

a gate insulation layer formed to wrap the each narrow trench gate and the wide trench gate;

an insulating layer covered on the source regions;

a source metal covered on the insulating layer;

a gate metal covered on the insulating layer isolated to the source;

a plurality of source contact plugs each of which is extended from the source metal and through the insulating layer to contact the corresponding source regions and the corresponding body region; and

at least a gate contact plug which is extended from the gate metal and through the insulating layer to contact the corresponding wide trench gate;

wherein the first type semiconductor which is one type of N-type semiconductor and P-type semiconductor, and the second type semiconductor is the other;

the source metal is electrically connected to the source regions and the body regions by the source contact plugs;

the gate metal is electrically connected to the wide trench gate by the gate contact plug; and

the wide trench gate is extended into the insulating layer covered on the top thereof so the polysilicon in the wide trench.

2. The MOSFET of claim 1, wherein an underneath doped area which is heavily doped with the first type semiconductor underneath each bottom of the narrow trenched gates and the wide trench gate.

3. The MOSFET of claim 1, wherein further comprises a contact implantation part at the bottom of each source contact plug, and the contact implantation part is carried out by the second semiconductor type doping with higher doping concentration than the body region.

4. The MOSFET of claim 1, wherein further comprises a backside metal disposed on backside of said substrate as drain regions.

5. The MOSFET of claim 1, wherein further comprises a plurality of floating trench rings serving as termination.

6. The MOSFET of claim 1, wherein the polysilicon in the gate of the narrow trench gates and the wide trench gate is chosen from doped polysilicon.

7. The MOSFET of claims 1, wherein the polysilicon in the gate of the narrow trench gates and the wide trench gate is chosen from a combination of doped polysilicon and non-doped polysilicon.