TRANSISTOR STRUCTURE HAVING DUAL SHIELD LAYERS

• US 20100090273A1
• Filed: 10/09/2008
• Published: 04/15/2010
• Est. Priority Date: 10/09/2008
• Status: Active Grant

• Current Assignee: Xenogenic Development Limited Liability Company (Intellectual Ventures LLC)
• Original Assignee: HVVi Semiconductors Incorporated
• Inventors: Davies, Robert Bruce
• Granted Patent: US 8,008,719 B2
• Time in Patent Office: Days
• US Class Current: 257/329
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/2815 part or whole of the electrode is a sidewall spacer or made by a similar technique, e.g. transformation under mask, plating
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402

Abstract

A semiconductor device is formed having lower gate to drain capacitance. A trench (80) is formed adjacent to a drain (20) of the semiconductor device. Trench (80) has a sidewall surface (100) and a surface (90). A doped region (110) is implanted through the sidewall surface (100) of trench (80). A dielectric layer (150) overlies the sidewall surface (100) of trench (80). A shield layer (170) overlies the dielectric layer (150). The shield layer (170) is between a portion of drain (20) and a portion of the gate and gate interconnect of the semiconductor device thereby reducing gate to drain capacitance. The shield layer (170) overlies a minority portion of the surface (90) of trench (80). A second shield layer (270) further reduces gate to drain capacitance.

Claims

1. A device, comprising:

a transistor having a gate, a drain region, and a source region where the drain and the source region are of a first conductivity type;

a trench in proximity to the drain region of the device where the trench has a sidewall and a major surface;

a first dielectric layer overlying the sidewall and the major surface of the trench; and

a first conductive layer overlying the sidewall of the trench where the first conductive layer does not overlie a majority of the major surface of the trench.

2. The device of claim 1, further comprising:

a second dielectric layer overlying the first conductive layer; and

a second conductive layer overlying the second dielectric layer.

3. The device of claim 2, wherein the second conductive layer overlies the majority of the major surface of the trench.

4. The device of claim 3, wherein the first and second conductive layers are coupled together.

5. The device of claim 3, wherein the first dielectric layer and the second dielectric layer comprises silicon dioxide.

6. The device of claim 5, further comprising:

a third dielectric layer overlying a portion of the first dielectric layer and underlying a portion of the first conductive layer; and

a fourth dielectric layer overlying a portion of the second conductive layer and underlying a portion of the second dielectric layer.

7. The device of claim 6, wherein the third dielectric layer and the fourth dielectric layer comprises silicon nitride.

8. The device of claim 1, further comprising:

a first region comprising a sidewall doping in the drain region and comprising the first conductivity type in proximity to the sidewall of the trench;

a second region comprising surface doping in the drain region and comprising the first conductivity type in proximity to a major surface of the drain region; and

a tub region of a second conductivity type where the source region is formed in the tub region, where a portion of the tub region underlies the gate, and where the portion of the tub region that underlies the gate is a channel region of the device.

9. The device of claim 8, wherein the trench has a depth greater than a depth of the tub region.

10. The device of claim 8, further comprising a substrate of the first conductivity type and wherein the drain region comprises an epitaxial layer overlying the substrate.

11. A method of forming a trench region in a semiconductor substrate, the method comprising:

etching a trench in the substrate having a sidewall and a major surface;

depositing a first dielectric layer overlying the sidewall and the major surface of the trench;

depositing a first conductive layer overlying the first dielectric layer; and

etching at least a majority of the first conductive layer overlying the major surface of the trench.

12. The method of claim 11, further comprising depositing a second dielectric layer overlying the first conductive layer and at least a majority of the major surface of the trench.

13. The method of claim 11, further comprising implanting dopant through the sidewall and the major surface of the trench.

14. The method of claim 13, further comprising:

etching a portion of the first dielectric layer to expose at least a majority of the major surface of the trench; and

etching at least a majority of the major surface of the trench to remove implanted dopant.

15. The method of claim 11, further comprising:

etching a portion of the first dielectric layer to expose at least a majority of the major surface of the trench;

etching a second trench having a sidewall and a major surface; and

depositing a third dielectric layer overlying the sidewall and the major surface of the second trench.

16. The method of claim 12, further comprising:

exposing a portion of the first conductive layer in proximity to a surface of the substrate;

depositing a second conductive layer where the first and second conductive layers couple to one another; and

depositing a third dielectric layer overlying the second conductive layer.

17. A transistor, comprising:

a substrate of a first conductivity type;

an epitaxial layer of the first conductivity type overlying the substrate;

a trench in the epitaxial layer having a sidewall and a major surface;

a first shield layer overlying the sidewall of the trench and overlying a minority of the major surface of the trench; and

a pedestal overlying a portion of the epitaxial layer and a portion of the trench, the pedestal having a sidewall and a major surface.

18. The transistor as recited in claim 17, further comprising:

a polysilicon layer overlying the sidewall an major surface of the pedestal;

a tub region of a second conductivity type in the epitaxial layer wherein a portion of the tub region underlies a vertical portion of the polysilicon layer, wherein the vertical portion of the polysilicon layer is a gate of the transistor, and wherein the portion of the tub region underlying the gate is the channel region of the transistor; and

a source region of the first conductivity type in the tub region.

19. The transistor as recited in claim 18, wherein a drain of the transistor is the epitaxial layer and where the trench limits lateral current flow of the transistor.

20. The transistor as recited in claim 18, wherein at least one dielectric layer isolates the first shield layer from the sidewall.

21. The transistor as recited in claim 20, wherein the pedestal comprises at least three dielectric layers.

22. The transistor as recited in claim 21, further comprising a second shield layer where a portion of the second shield layer is between two of the at least three dielectric layers of the pedestal and where the second shield layer overlies a majority of the major surface of the trench.

23. The transistor as recited in claim 22, wherein the first and second shield layers are coupled together.

24. The transistor as recited claim 23, wherein the depth of the trench is greater than the depth of the tub.

25. The transistor as recited in claim 24, further comprising:

a first doped region of the first conductivity type in proximity to the sidewall of the trench; and

a second doped region in proximity to a major surface of the epitaxial layer.

26. The transistor as recited in claim 25, wherein a channel length of the transistor corresponds to the thickness of the polysilicon layer