TRENCH MOSFET WITH SHALLOW TRENCH CONTACT

• US 20100090274A1
• Filed: 10/10/2008
• Published: 04/15/2010
• Est. Priority Date: 10/10/2008
• Status: Abandoned Application

• Current Assignee: Force Mos Technology Co., Ltd.
• Original Assignee: Force Mos Technology Co., Ltd.
• Inventors: Hsieh, Fu-Yuan
• Application Number:
  US12/249,360
• Publication Number:
  US 20100090274A1
• Time in Patent Office: Days
• US Class Current: 257/331
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench MOSFET element with shallow trench contact is disclosed. This shallow trench contact structure has some advantages: blocking the P+ underneath trench contact from lateral diffusion to not touch to channel region when a larger trench contact CD is applied; avoiding the trench gate contact etching through poly and gate oxide when trench gate becomes shallow; making lower cost to refill the trench contact using Al alloys with good metal step coverage as the trench contact is shallower. The disclosed trench MOSFET element further includes an n* region around the bottom of gate trenches to reduce Rds. In some embodiment, the disclosed trench MOSFET provides a terrace gate to further reduce Rg and make self-aligned source contact; In some embodiment, the disclosed trench MOSFET comprises a P* area underneath said P+ region for avalanche energy improvement with lighter dose than said P+ region.

Claims

1. A vertical semiconductor power MOS device comprising a plurality of semiconductor power cells with each cell comprising a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate, wherein said MOS cell further comprising:

a low-resistivity substrate to reduce Rds;

a plurality of trench gates and at least a wider trench gate for gate contact;

a plurality of floating trench gates as termination rings;

a doped area underneath said trench bottom with the same doping type as epitaxial layer but doping concentration is heavier than epitaxial layer, to further reduce Rds;

a source-body contact trench opened through a contact oxide layer covering said cell structure and extending into said body region with the contact trench depth in epitaxial layer shallower than source junction depth;

a gate contact trench opened through said insulating layer and extending into trench-filling material in said trenched gate underneath gate runner metal;

a source metal and gate metal layer formed on a top surface of the MOSFET; and

a drain metal layer formed on a bottom surface of the MOSFET.

2. The MOSFET of claim 1, the substrate is phosphorus doped with resistivity less than 2.0 mohm-cm.

3. The MOFET of claim 1 has heavily doped layer underneath source-body contact trench with doping type same as said body layer for ohmic contact and avalanche current enhancement. The dose of said heavily doped layer ranges from 5E14 to 4E15. cm−

2.

4. The MOFET of claim 1 has a doped layer underneath said the heavily doped layer with doping type same as said body layer for further improving avalanche current. The dose of said doped layer ranges from 1E13 to 1E14 cm−

2.

5. The MOSFET of claim 1 wherein said trench-filling material is doped poly.

6. The MOSFET of claim 1 wherein said trench-filling material is combination of doped poly and non-doped poly.

7. The MOSFET of claim 1 wherein said trench-filling material is doped poly with silicide on the poly top.

8. The MOSFET of claim 1 wherein said trench-filling material is doped poly with silicide inside the doped poly.

9. The MOSFET of claim 1 wherein said trench contact is filled with Ti/TiN/W, Co/TiN/W or Mo/Ti/W connected with Al Alloys as source and gate metal.

10. The MOSFET of claim 1 wherein said trench contact is filled with Ti/TiN/Al Alloys, Co/TiN/Al alloys or Mo/TiN/Al alloys as source and gate metal.

11. A method for manufacturing a trench MOSFET with shallow trench contact comprising the steps of:

growing an epitaxial layer upon a heavily N doped substrate, wherein said epitaxial layer is doped with a first type dopant, eg., N dopant;

forming a trench mask with open and closed areas on the surface of said epitaxial layer;

removing semiconductor material from exposed areas of said trench mask to form a plurality of gate trenches;

depositing a sacrificial oxide layer onto the surface of said trenches to remove the plasma damage introduced during opening said trenches;

removing said sacrificial oxide and said trench mask;

implanting whole device with Arsenic ion to form n* area underneath each gate trench;

depositing gate oxide on the surface of said epitaxial layer and along the inner surface of said gate trenches;

depositing a layer of doped poly or combination doped poly and non-doped poly onto said gate oxide and into said gate trenches;

etching back or CMP said doped poly or combination doped poly and non-doped poly from the surface of said gate oxide and leaving enough doped poly or combination doped poly and non-doped poly into said gate trenches to serve as trench gate material;

forming silicide on top poly as alternative for low Rg;

implanting said epitaxial layer with a second type dopant to form P-body regions;

depositing a source mask with open and closed areas to define n+ source regions;

implanting whole device with a first type dopant to form source regions;

removing said source mask and forming a thick contact oxide onto whole surface;

forming a contact mask on the surface of said contact oxide layer and removing oxide material and semiconductor material, as well as poly material from exposed areas of said contact mask to open a plurality of contact trenches;

driving in n+ ion of source region by n+ source diffusion to make n+ junction deeper than the trench source contact in silicon;

implanting BF 2 ion to form P+ area underneath source contact trench and body contact trench;

depositing Ti/TiN/W consequently into contact trenches and on the front surface;

etching back W and Ti/TiN to form contact metal plug and depositing a layer of Ti or TiN and then a layer of Al alloys whereon; and

forming a metal mask onto said Al alloys with open and closed areas and removing metal material from the exposed areas of said metal mask to form interconnection metal and front metal.

12. The method of claim 11, wherein forming said gate trenches comprises etching said epitaxial layer according to the open areas of said trench mask.

13. The method of claim 11, wherein forming said P-body regions comprises a step of diffusion to achieve a certain after P-body implantation step.

14. The method of claim 11, wherein forming said contact trenches comprise etching through said contact oxide and said gate oxide by dry oxide etching according to the exposed areas of said contact mask.

15. The method of claim 11, wherein forming said contact trenches comprise etching into n+ source region and p-body region by dry silicon etching according to the exposed areas of said contact mask.

16. The method of claim 11, wherein forming said contact trenches comprise etching into doped poly or combination of doped poly and non-doped poly by dry poly etching according to the exposed areas of said contact mask.

17. The method of claim 11, wherein forming said contact trenches comprises forming terrace contact trenches.

18. The method of claim 17, wherein forming said terrace contact trenches comprises forming terrace source contact trench and terrace body contact trench.

19. The method of claim 18, wherein forming said terrace source and body contact trenches comprises forming terrace contact with contact width near the surface of contact oxide larger than contact width in source portion.

20. The method of claim 11, wherein forming said P+ area underneath source contact trench and body contact trench comprises forming said P+ area with a concentration of 5E14˜

2E15 cm<sup>−

2</sup> under 20˜

60 KeV.

21. The method of claim 11, after the formation of P+ area underneath source contact trench and body contact trench, a Boron Ion Implantation is followed to form P* region under P+ area for further enhancing avalanche current.

22. The method of claim 21, wherein forming said P* region comprises forming said P* region with a concentration of 1E13˜

1E14 cm<sup>−

2</sup> under 100˜

200 KeV.

23. The method of claim 11, wherein forming said interconnection metal and front metal comprises etching Al Alloys and Ti or TiN by dry metal etching according to the exposed areas of said metal mask.

24. The method of claim 11, wherein forming said contact plug comprises refilling contact trenches with Al Alloys to serve as contact metal and front metal.