Circuit and method of adjusting system clock in low voltage detection, and low voltage reset circuit

• US 20100090730A1
• Filed: 10/01/2009
• Published: 04/15/2010
• Est. Priority Date: 10/09/2008
• Status: Active Grant

• Current Assignee: Realtek Semiconductor Corp.
• Original Assignee: Realtek Semiconductor Corp.
• Inventors: Wu, Wen-Che
• Granted Patent: US 8,847,649 B2
• Time in Patent Office: Days
• US Class Current: 327/143
• CPC Class Codes: G06F 1/24 Resetting means
• CPC Class Codes: G06F 1/305 in the event of power-supply fluctuations
• CPC Class Codes: H03K 19/00369 Modifications for compensating variations of temperature, supply voltage or other physical parameters
• CPC Class Codes: H03L 5/02 of power

Abstract

The present invention discloses a circuit and a method of adjusting system clock in low voltage detection, and a low voltage reset circuit. The circuit of adjusting system clock in low voltage detection comprises: a clock generator for supplying a clock to at least one circuit in a system; and a low voltage reset circuit for generating an adjustment signal according to a detected voltage level, so that the clock generator adjusts or stops the clock supplied to the at least one circuit in the system.

Claims

1. A circuit of adjusting system clock in low voltage detection,. comprising:

a clock generator for supplying a clock to at least one circuit in a system; and

a low voltage reset circuit for generating an adjustment signal according to a detected voltage level, so that the clock generator adjusts or stops the clock supplied to the at least one circuit in the system.

2. The circuit of claim 1, wherein the low voltage reset circuit detects a voltage level of a supplied voltage, and when the voltage level is lower than a predetermined first threshold value, the low voltage reset circuit generates the adjustment signal.

3. The circuit of claim 2, wherein the low voltage reset circuit stops generating the adjustment signal when the voltage level is lower than a predetermined second threshold value.

4. The circuit of claim 2, wherein the low voltage reset circuit generates a reset signal when the voltage level is lower than a predetermined second threshold value, such that the at least one circuit in the system is reset to a predetermined value.

5. The circuit of claim 4, wherein the low voltage reset circuit stops generating the reset signal when the voltage level is lower than a predetermined third threshold value.

6. The circuit of claim 2, wherein the first threshold value is a lower limit of a normal operation voltage.

7. The circuit of claim 1, wherein the clock generator generates two series of clocks, and the clock generator adjusts or stops one series of clocks but still provides the other series of clocks when the low voltage reset circuit generates the adjustment signal.

8. A method of adjusting system clock in low voltage detection, comprising:

detecting a level of a supplied voltage; and

generating an adjustment signal to control a clock generator according to the detection result.

9. The method of claim 8, wherein the clock generator adjusts or stops a clock when receiving the adjustment signal.

10. The method of claim 8, wherein the clock generator generates two series of clocks, and the clock generator adjusts or stops one series of clocks but still provides the other series of clocks when it receives the adjustment signal.

11. The method of claim 8, wherein the adjustment signal is generated when the level of the supplied voltage is lower than a predetermined first threshold value.

12. The method of claim 11, wherein the adjustment signal is not generated when the level of the supply voltage is lower than a predetermined second threshold value.

13. The method of claim 11, further comprising:

generating a reset signal when the level of the supplied voltage is lower than a predetermined second threshold value, such that at least one circuit is reset to a predetermined value.

14. The method of claim 13, wherein the reset signal is stopped when the level of the supplied voltage is lower than a predetermined third threshold value.

15. The method of claim 11, wherein the first threshold value is a lower limit of a normal operation voltage.

16. A low voltage reset circuit comprising:

a voltage division circuit dividing a supplied voltage to generate multiple reference voltages;

a comparator circuit comparing a voltage signal related to the supplied voltage with the multiple reference voltages; and

a logic circuit determining whether to generate an adjustment signal according to the comparison result.

17. The low voltage reset circuit of claim 16, wherein the logic circuit further decides whether to generate a reset signal according to the comparison result.

18. The low voltage reset'"'"'circuit of claim 16, wherein the adjustment signal is generated when a level of the supplied voltage is lower than a predetermined first threshold value.

19. The low voltage reset circuit of claim 16, wherein the adjustment signal is not generated when a level of the supplied voltage is lower than a predetermined second threshold value.

20. The low voltage reset circuit of claim 17, wherein the reset signal is generated when the level of the supplied voltage is lower than a predetermined second threshold value.

21. The low voltage reset circuit of claim 17, wherein the reset signal is not generated when the level of the supplied voltage is lower than a predetermined third threshold value.