SEMICONDUCTOR MEMORY DEVICE

• US 20100091547A1
• Filed: 09/03/2009
• Published: 04/15/2010
• Est. Priority Date: 10/14/2008
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Ogiwara, Ryu, Takashima, Daisaburo
• Granted Patent: US 8,045,357 B2
• Time in Patent Office: Days
• US Class Current: 365/145
• CPC Class Codes: G11C 11/22 using ferroelectric elements

Abstract

A memory includes a memory cell array including destructive read-out type memory cells; a decoder selecting a cell; a sense amplifier configured to detect the data; and a read and write controller controlling a read operation and a write operation, wherein the read and write controller outputs a logical value of a write enable signal at the start of the read operation in a first period and makes the write enable signal invalid after the read operation starts during the first period, on the basis of the write enable signal and a restore signal keeping an activated state during the first period, the write enable signal being a signal allowing the write operation, the first period being a period from when the read operation starts to when a restore operation for writing the data back to the memory cell is completed.

Claims

1. A semiconductor memory device comprising:

a memory cell array configured by two-dimensionally arranging destructive read-out type memory cells that stored data is degraded by data read;

a decoder configured to select a memory cell in the memory cell array;

a sense amplifier configured to detect the data stored in the selected memory cell; and

a read and write controller configured to control a read operation for reading data externally from the memory cell and a write operation for writing external data in the memory cell, wherein

the read and write controller outputs a logical value of a write enable signal at the start of the read operation in a first period and makes the write enable signal invalid after the read operation starts during the first period, on the basis of the write enable signal and a restore signal keeping an activated state during the first period, the write enable signal being a signal allowing the write operation, the first period being a period from when the read operation starts to when a restore operation for writing the data back to the memory cell is completed.

2. The device of claim 1, wherein the sense amplifier starts the read operation and the restore signal is activated when an externally supplied chip enable signal is activated under the write enable signal being in an inactivated state, and

the read and write controller comprises a logical part configured to receive the write enable signal and the restore signal and to perform a logical operation of them in order to output continuously the logical value of the write enable signal at the start of the read operation during the first period.

3. The device of claim 1, wherein the sense amplifier starts the data read operation and the restore signal is activated when an externally supplied clock signal is activated under the write enable signal being in an inactivated state, and

the read and write controller comprises a logical part configured to receive the write enable signal and the restore signal and to perform a logical operation of them in order to output continuously the logical value of the write enable signal at the start of the data read operation during the first period.

4. The device of claim 2, wherein the restore signal is inactivated before the chip enable signal is inactivated, and

the read and write controller activates the write enable signal at any time point before the chip enable signal is inactivated after the restore signal has been inactivated, in such a manner that the data write operation can be performed.

5. The device of claim 3, wherein the restore signal is inactivated before the chip enable signal is inactivated, and

the read and write controller activates the write enable signal at any time point before the chip enable signal is inactivated after the restore signal has been inactivated, in such a manner that the data write operation can be performed.

6. A memory system comprising:

the semiconductor memory device according to claim 1; and

a power supply circuit configured to keep a power supply voltage to be supplied to the semiconductor memory device at a certain voltage or higher during the first period, wherein

the power supply circuit comprises;

a switch between an external power supply and the semiconductor memory device;

a stabilizing capacity connected to a node between the switch and the semiconductor memory device; and

a power supply monitoring circuit configured to receive a voltage of the external power supply and a reference power supply voltage and to compare the external power supply voltage to the reference power supply voltage, the reference power supply voltage serving as a threshold for the external power supply voltage,

wherein the power supply monitoring circuit turns off the switch when the external power supply voltage gets across the reference power supply voltage.

7. A memory system comprising:

the semiconductor memory device according to claim 2; and

a power supply circuit configured to keep a power supply voltage to be supplied to the semiconductor memory device at a certain voltage or higher during the first period, wherein

the power supply circuit comprises;

a switch between an external power supply and the semiconductor memory device;

a stabilizing capacity connected to a node between the switch and the semiconductor memory device; and

a power supply monitoring circuit configured to receive a voltage of the external power supply and a reference power supply voltage and to compare the external power supply voltage to the reference power supply voltage, the reference power supply voltage serving as a threshold for the external power supply voltage,

wherein the power supply monitoring circuit turns off the switch when the external power supply voltage gets across the reference power supply voltage.

8. A memory system comprising:

the semiconductor memory device according to claim 3; and

a power supply circuit configured to keep a power supply voltage to be supplied to the semiconductor memory device at a certain voltage or higher during the first period, wherein

the power supply circuit comprises;

a switch between an external power supply and the semiconductor memory device;

a stabilizing capacity connected to a node between the switch and the semiconductor memory device; and

a power supply monitoring circuit configured to receive a voltage of the external power supply and a reference power supply voltage and to compare the external power supply voltage to the reference power supply voltage, the reference power supply voltage serving as a threshold for the external power supply voltage,

wherein the power supply monitoring circuit turns off the switch when the external power supply voltage gets across the reference power supply voltage.

9. A memory system comprising:

the semiconductor memory device according to claim 4; and

a power supply circuit configured to keep a power supply voltage to be supplied to the semiconductor memory device at a certain voltage or higher during the first period, wherein

the power supply circuit comprises;

a switch between an external power supply and the semiconductor memory device;

a stabilizing capacity connected to a node between the switch and the semiconductor memory device; and

a power supply monitoring circuit configured to receive a voltage of the external power supply and a reference power supply voltage and to compare the external power supply voltage to the reference power supply voltage, the reference power supply voltage serving as a threshold for the external power supply voltage,

wherein the power supply monitoring circuit turns off the switch when the external power supply voltage gets across the reference power supply voltage.