PACKET SWITCHING SYSTEM

• US 20100091775A1
• Filed: 11/17/2009
• Published: 04/15/2010
• Est. Priority Date: 06/04/2007
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Yamamoto, Kanta
• Granted Patent: US 8,621,325 B2
• Time in Patent Office: Days
• US Class Current: 370/392
• CPC Class Codes: H04L 45/68 Pseudowire emulation, e.g. IETF WG PWE3
• CPC Class Codes: H04L 49/25 Routing or path finding in a switch fabric

Abstract

A packet switching system includes a forwarding processing unit determining a destination of an input packet by analyzing the input packet and outputting it as an output packet, the forwarding processing unit comprises an ingress interface card checking if the input packet has a sequential cyclic number and an egress interface card creating a sequential cyclic number and assigning it to the output packet.

Claims

1. A packet switching system comprising a forwarding processing unit determining a destination of an input packet by analyzing the input packet and outputting it as an output packet, the forwarding processing unit comprises an ingress interface card checking if the input packet has a sequential cyclic number and an egress interface card creating a sequential cyclic number and assigning it to the output packet.

2. The packet switching system as set forth in claim 1, wherein the ingress interface card comprises a check control memory of the sequential cyclic numbers and a first memory interface unit and second memory interface unit, acting for dividing one access processing to the check control memory into two by performing the processing at a consecutive first and second memory access point, and the forwarding processing unit judges, after processing at the first access point by the first memory interface unit, if correction is necessary on the results of processing by the first memory interface unit, and the second memory interface unit corrects the sequence number read from an address space of the check control memory at the second access point and writes it to the address space of the check control memory when it is judged by the forwarding processing unit that correction is necessary.

3. The packet switching system as set forth in claim 2, wherein the first memory interface unit comprises a processing unit running consecutively processing, at the first access point using the input packet header information as an address, to access the address space corresponding to the address of the check control memory and read the corresponding sequence number stored in the check control memory, processing for adding 1 to the sequence number read by the reading processing, and processing writing back the results of addition by the addition processing to the address space of the check control memory.

4. The packet switching system as set forth in claim 2, wherein the forwarding processing unit further comprises a receiving port attribute table for judging if the receiving port of the input packet is for pseudo wires, looks up the receiving port attribute table using the input physical port information, as an address, assigned to each input packet, and executes access to the check control memory only when the receiving port is for pseudo wires.

5. The packet switching system as set forth in claim 4, wherein the forwarding processing unit further comprises a sequence number presence table for running a check, using the header of the input packet as an address, on whether the input packet has a control word of a virtual frame and executes access to the check control memory only when the input packet is judged to have the control word.

6. The packet switching system as set forth in claim 5, wherein the sequence number presence table further comprises a function of running a check on whether the control word contains the sequence number and executes access to the check control memory only when the control word is judged to contain the sequence number.

7. The packet switching system as set forth in claim 2, wherein when the forwarding processing unit judges correction to be necessary, the second memory interface unit corrects, at the second access point, the sequence number newly read from the address space of the check control memory and writes it to the address space of the check control memory.

8. The packet switching system as set forth in claim 2, further comprising a pipeline configuration wherein the first memory access point, the forwarding processing unit, and the second memory access point are sequentially arranged.

9. The packet switching system as set forth in claim 2, wherein when the forwarding processing unit detects that the sequence number of the input packet is out-of-sequence following the results of processing by the first memory interface unit, the second memory interface unit writes the sequence number of the out-of-sequence input packet to the check control memory.

10. The packet switching system as set forth in claim 2, wherein the second memory interface unit is realized by software.

11. The packet switching system as set forth in claim 10, wherein the processing by the forwarding processing unit is realized by software contained in a monitoring control unit.

12. The packet switching system as set forth in claim 2, wherein the egress interface card comprises a check control memory of the cyclic numbers and a first memory interface unit and second memory interface unit acting for dividing one access processing to the check control memory into two by performing the processing at a consecutive first and second memory access point, and the forwarding processing unit judges, after processing at the first access point by the first memory interface unit, if correction is necessary on the results of processing by the first memory interface unit, and the second memory interface unit corrects the sequence number read from an address space of the check control memory at the second access point and writes it to the address space of the check control memory when it is judged by the forwarding processing unit that correction is necessary.

13. The packet switching system as set forth in claim 12, wherein the first memory interface unit comprises a processing unit running consecutively processing, at the first access point using the input packet header information as an address, to access the address space corresponding to the address of the check control memory and read the corresponding sequence number stored in the check control memory, processing for adding 1 to the sequence number read by the reading processing, and processing writing back the results of addition by the addition processing to the address space of the check control memory.

14. The packet switching system as set forth in claim 12, wherein the forwarding processing unit further comprises a sending port attribute table for judging if the sending port of the output packet is for pseudo wires, looks up the sending port attribute table using the output physical port information, as an address, assigned to each output packet, and executes access to the check control memory only when the sending port is for pseudo wires.

15. The packet switching system as set forth in claim 14, wherein the forwarding processing unit further comprises a sequence number presence table for running a check, using the header of the output packet as an address, on whether the output packet has a control word of virtual frame and executes access to the check control memory only when the output packet is judged to have the control word.

16. The packet switching system as set forth in claim 15, wherein the sequence number presence table further comprises a function for running a check on whether the control word contains the sequence number and executes access to the check control memory only when the control word is judged to contain the sequence number.

17. The packet switching system as set forth in claim 12, wherein when the forwarding processing unit judges correction to be necessary, the second memory interface unit corrects, at the second access point, the sequence number newly read from the address space of the check control memory and writes it to the address space of the check control memory.

18. The packet switching system as set forth in claim 12, further comprising a pipeline configuration wherein the first memory access point, the forwarding processing unit, and the second memory access point are sequentially arranged.

19. The packet switching system as set forth in claim 12, wherein the second memory interface unit is realized by software.

20. The packet switching system as set forth in claim 19, wherein the processing by the forwarding processing unit is realized by software contained in a monitoring control unit.

21. The packet switching system as set forth in claim 1, wherein the forwarding processing unit is realized by at least one hardware from among LSI and FPGA.

22. A packet switching system as set forth in claim 1, wherein the forwarding processing unit is realized by a programmable chip.

23. A packet switching system as set forth in claim 1, wherein the forwarding processing unit is realized by software.

24. A packet switching system as set forth in claim 1, the system is applied to check control or creation control for 16-bit sequence numbers contained in a pseudo wire control word.