Method and System for Controlling a Delay of Packet Processing Using Loop Paths

• US 20100091782A1
• Filed: 10/10/2008
• Published: 04/15/2010
• Est. Priority Date: 10/10/2008
• Status: Active Grant

• Current Assignee: Valtrus Innovations Limited (f/k/a Dolya Holdco 9 Limited) (Key Patent Innovations Limited)
• Original Assignee: 3Com Corporation (HP Inc.)
• Inventors: Hiscock, James S.
• Granted Patent: US 9,270,595 B2
• Time in Patent Office: Days
• US Class Current: 370/412
• CPC Class Codes: H04L 47/10 Flow control; Congestion control
• CPC Class Codes: H04L 47/283 in response to processing delays, e.g. caused by jitter or round trip time [RTT]
• CPC Class Codes: H04L 47/32 by discarding or delaying data units, e.g. packets or frames
• CPC Class Codes: H04L 47/34 ensuring sequence integrity, e.g. using sequence numbers
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/9094 Arrangements for simultaneous transmit and receive, e.g. simultaneous reading/writing from/to the storage element

Abstract

A method and system for introducing controlled delay of packet processing at a network device using one or more delay loop paths (DLPs). For each packet received at the network device, a determination will be made as to whether or not packet processing should be delayed. If delay is chosen, a DLP will be selected according to a desired delay for the packet. The desired delay value is used to determine a time value and inserts the time value in the DLP ahead of the packet. Upon completion of a DLP delay, a packet will be returned for processing, an additional delay, or some other action. One or more DLPs may be enabled with packet queues, and may be used advantageously by devices, for which in-order processing of packets may be desired or required.

Claims

1. A method of introducing controlled delay in the processing of packets in a packet-switched data network, the method comprising:

determining that a packet should be delayed before being processed;

determining a desired delay value for the packet;

associating a time value with the packet based on the desired delay value;

sending the packet on a delay loop path (DLP); and

removing the packet from the DLP when the time value indicates.

2. The method of claim 1, wherein the removing further comprises;

comparing the time value to a system time and;

removing the packet if the time value is a time less than or equal to the system time.

3. The method of claim 1, wherein sending the packet on the DLP comprises inserting the packet in an ordered list of packets.

4. The method of claim 3, wherein the ordered list of packets is ordered by the time value associated with the packet on the DLP.

5. The method of claim 1, wherein sending the packet on the DLP comprises:

adding the packet to a FIFO; and

wherein associating a time value with the packet further comprises;

writing the time value to the FIFO before writing the packet to the FIFO.

6. The method of claim 1, wherein sending the packet on the DLP further comprises:

selecting one of multiple FIFOs;

adding the packet to the selected FIFO; and

wherein the associating a time value with the packet further comprises;

writing the time value to the FIFO before writing the packet to the FIFO.

7. The method of claim 6, wherein the selecting one of multiple FIFOs further comprises:

comparing an assigned delay value for each DLP with the desired delay value of the packet; and

selecting a FIFO having an assigned delay value that is closest in value to the desired delay.

8. The method of claim 1, wherein the determining that the packet should be delayed further comprises:

determining at least one property of the packet.

9. The method of claim 8, wherein determining at least one property of the packet comprises:

inspecting data in the packet; and

determining a relationship of the packet with one or more previously received packets.

10. The method of claim 9, wherein determining the at least one property of the packet further comprises:

determining that the packet is one of a plurality of packets in an ordered sequence and that the packet is out of order with respect to at least one other packet in the ordered sequence.

11. The method of claim 9, wherein determining the at least one property of the packet further comprises:

determining that the packet is one of a plurality of packets in a sequence and that the packet should be delayed to pace the traffic of the packet sequence.

12. A packet processing apparatus with packet delay circuitry comprising:

a first logic unit that determines that a packet should be delayed before the packet is processed or forwarded;

a second logic unit that determines a desired delay value for the packet;

a third logic unit that associates a time value with the packet;

a forth logic unit that sends the packet on a delay loop path (DLPA;

at least one DLP; and

a fifth logic unit that removes the packet from the DLP when the time value indicates.

13. A packet processing apparatus of claim 12, wherein the first, second, third, fourth, and fifth logic units and DLPs are implemented in an FPGA.

14. A packet processing apparatus of claim 12, wherein the first, second, third, fourth, and fifth logic units are implemented in an ASIC.

15. A packet processing apparatus of claim 12, wherein the first, second, third, fourth, and fifth logic units and DLPs are implemented as a combination of hardware and software.

16. A packet processing apparatus of claim 12, wherein the DLP is implemented as an ordered list of packets.

17. A packet processing apparatus of claim 12, wherein one or more DLPs are each implemented as a FFO.

18. A packet processing apparatus of claim 12, wherein the packet processing apparatus is an IPS.

19. A packet processing apparatus of claim 12, wherein the packet processing apparatus connects a public network to a local area network (LAN).

20. A packet processing apparatus of claim 12, wherein the packet processing apparatus is a VPN device.

21. A packet processing apparatus of claim 12, wherein the packet processing apparatus is an Ethernet switch.

22. A packet processing apparatus of claim 12, wherein the packet processing apparatus is a firewall.

23. A packet processing apparatus of claim 12, wherein the packet processing apparatus is an intelligent network adapter.