LIGHT EMITTING DEVICE HAVING LIGHT EXTRACTION STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

• US 20100093123A1
• Filed: 12/14/2009
• Published: 04/15/2010
• Est. Priority Date: 05/08/2006
• Status: Active Grant

• Current Assignee: Suzhou Lekin Semiconductor Company Limited
• Original Assignee: Hyun Kyong Cho, Jun H.O. Jang, Sun Kyung Kim
• Inventors: JANG, Jun Ho, CHO, Hyun Kyong, KIM, Sun Kyung
• Granted Patent: US 8,008,103 B2
• Time in Patent Office: Days
• US Class Current: 438/42
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48257 connecting the wire to a die pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2933/0016 relating to electrodes
• CPC Class Codes: H01L 2933/0033 relating to semiconductor body packages
• CPC Class Codes: H01L 2933/0083 Periodic patterns for optical field-shaping in or on the semiconductor body or semiconductor body package, e.g. photonic bandgap structures
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/20 with a particular shape, e.g. curved or truncated substrate
• CPC Class Codes: H01L 33/22 Roughened surfaces, e.g. at the interface between epitaxial layers
• CPC Class Codes: H01L 33/405 Reflective materials
• CPC Class Codes: H01L 33/42 Transparent materials
• CPC Class Codes: H01L 33/44 characterised by the coatings, e.g. passivation layer or anti-reflective coating
• CPC Class Codes: H01L 33/48 characterised by the semiconductor body packages
• CPC Class Codes: H01L 33/60 Reflective elements
• CPC Class Codes: H01L 33/62 Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
• CPC Class Codes: Y10S 438/977 : Thinning or removal of substrate

Abstract

A nitride-based light emitting device capable of achieving an enhancement in emission efficiency and an enhancement in reliability is disclosed. The light emitting device includes a semiconductor layer, and a light extracting layer arranged on the semiconductor layer and made of a material having a refractive index equal to or higher than a reflective index of the semiconductor layer.

Claims

1. A method for manufacturing a light emitting device, comprising:

growing a semiconductor structure having multi-layers over a substrate;

forming a first electrode over the semiconductor structure;

removing the substrate;

forming a dielectric layer over a surface of the semiconductor structure exposed by the removal of the substrate;

forming a plurality of holes in the dielectric layer;

forming a plurality of grooves in the semiconductor structure by using the dielectric layer as a mask;

removing the dielectric layer; and

forming a second electrode over the surface of the semiconductor structure.

2. The method according to claim 1, wherein growing the semiconductor structure comprises:

forming an n-type semiconductor layer over the substrate;

forming an active layer over the n-type semiconductor layer; and

forming a p-type semiconductor layer over the active layer.

3. The method according to claim 1, wherein the dielectric layer comprises an oxide or a nitride.

4. The method according to claim 2, wherein the grooves are formed with a depth corresponding to ⅓

or more of a thickness of the n-type semiconductor layer exposed by the removal of the substrate.

5. The method according to claim 1, wherein the holes or the grooves are formed with a regular pattern.

6. The method according to claim 1, wherein forming the plurality of holes or forming the plurality of grooves is carried out by using a dry etching process.

7. The method according to claim 6, wherein the dry etching process is a reactive ion etching (RIE) process or an inductively-coupled plasma reactive ion etching (ICP-RIE) process.

8. The method according to claim 6, wherein the dry etching process is performed by using at least one of Ar, BCl₃, Cl₂, CF₄, and CHF₃.

9. The method according to claim 1, wherein forming the plurality of holes in the dielectric layer is performed by forming the holes in a region where the second electrode is not to be formed.

10. The method according to claim 9, wherein forming the second electrode is formed on the region.