NON-VOLATILE RESISTIVE SENSE MEMORY ON-CHIP CACHE
First Claim
1. An apparatus comprising a first semiconductor substrate on which is formed a processing circuit, and a second semiconductor substrate affixed to the first semiconductor substrate to form an encapsulated integrated chip package, wherein a non-volatile storage array of resistive sense memory (RSM) cells is formed on the second semiconductor substrate to cache data used by the processing circuit.
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Accused Products
Abstract
Various embodiments of the present invention are generally directed to an apparatus and associated method for a non-volatile resistive sense memory on-chip cache. In accordance with some embodiments, a processing circuit is formed on a first semiconductor substrate. A second semiconductor substrate is affixed to the first semiconductor substrate to form an encapsulated integrated chip package, wherein a non-volatile storage array of resistive sense memory (RSM) cells is formed on the second semiconductor substrate to cache data used by the processing circuit.
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Citations
20 Claims
- 1. An apparatus comprising a first semiconductor substrate on which is formed a processing circuit, and a second semiconductor substrate affixed to the first semiconductor substrate to form an encapsulated integrated chip package, wherein a non-volatile storage array of resistive sense memory (RSM) cells is formed on the second semiconductor substrate to cache data used by the processing circuit.
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11. A method comprising:
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providing a first semiconductor substrate on which is formed a processing circuit; affixing a second semiconductor substrate to the first semiconductor substrate to form an encapsulated integrated chip package, wherein a non-volatile storage array of resistive sense memory (RSM) cells is formed on the second semiconductor substrate to cache data used by the processing circuit. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification