NON-VOLATILE RESISTIVE SENSE MEMORY ON-CHIP CACHE

• US 20100095057A1
• Filed: 10/15/2008
• Published: 04/15/2010
• Est. Priority Date: 10/15/2008
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Huang, Henry F., Li, Hai, Liu, Hongyue, Chen, Yiran
• Granted Patent: US 8,650,355 B2
• Time in Patent Office: Days
• US Class Current: 711/104
• CPC Class Codes: G06F 12/0893 Caches characterised by their organisation or structure
• CPC Class Codes: G06F 2212/2024 Rewritable memory not requiring erasing, e.g. resistive or ferroelectric RAM
• CPC Class Codes: G06F 2212/222 Non-volatile memory
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 15/02 using magnetic elements
• CPC Class Codes: G11C 15/046 using non-volatile storage elements
• CPC Class Codes: G11C 2211/5643 Multilevel memory comprising cache storage devices
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: G11C 8/10 Decoders

Abstract

Various embodiments of the present invention are generally directed to an apparatus and associated method for a non-volatile resistive sense memory on-chip cache. In accordance with some embodiments, a processing circuit is formed on a first semiconductor substrate. A second semiconductor substrate is affixed to the first semiconductor substrate to form an encapsulated integrated chip package, wherein a non-volatile storage array of resistive sense memory (RSM) cells is formed on the second semiconductor substrate to cache data used by the processing circuit.

Claims

1. An apparatus comprising a first semiconductor substrate on which is formed a processing circuit, and a second semiconductor substrate affixed to the first semiconductor substrate to form an encapsulated integrated chip package, wherein a non-volatile storage array of resistive sense memory (RSM) cells is formed on the second semiconductor substrate to cache data used by the processing circuit.

2. The apparatus of claim 1, wherein the RSM cells of the storage array each comprise a spin-torque transfer random access memory (STRAM) cell.

3. The apparatus of claim 1, wherein the RSM cells of the storage array each comprise a resistive random access memory (RRAM) cell.

4. The apparatus of claim 1, wherein the processing circuit of the first semiconductor substrate comprises a CPU core and an L1 cache, and wherein the storage array of the second semiconductor substrate comprises an L2 cache.

5. The apparatus of claim 1, wherein the storage array comprises a word memory array and an index array, wherein the storage array is configured to output word data from the word memory array during a data retrieval operation when input request data matches tag data stored in the index array.

6. The apparatus of claim 5, wherein the storage array further comprises a volatile index array formed of volatile memory cells, wherein the tag data are concurrently stored in the respective volatile index array and the non-volatile index array, and wherein the tag data stored in the non-volatile index array are copied to the volatile index array upon a reinitialization operation.

7. The apparatus of claim 1, wherein the RSM cells are configured as content addressable memory (CAM) cells.

8. The apparatus of claim 1, wherein during a data write operation, new word data are written to a word memory array of the storage array and new tag data associated with the new word data are concurrently written to a corresponding index array of the storage array.

9. The apparatus of claim 1, wherein the storage array of the second semiconductor substrate comprises a cache in a pipeline memory structure of a data storage device with a non-volatile main memory.

10. The apparatus of claim 1, wherein the second semiconductor substrate is standardized to interchangeably affix to a third semiconductor substrate on which is formed a second processing circuit with a hardware configuration different from the processing circuit of the first semiconductor substrate to form a different encapsulated integrated chip package.

11. A method comprising:

providing a first semiconductor substrate on which is formed a processing circuit;

affixing a second semiconductor substrate to the first semiconductor substrate to form an encapsulated integrated chip package, wherein a non-volatile storage array of resistive sense memory (RSM) cells is formed on the second semiconductor substrate to cache data used by the processing circuit.

12. The method of claim 11, wherein the RSM cells of the storage array each comprise a spin-torque transfer random access memory (STRAM) cell.

13. The method of claim 11, wherein the RSM cells of the storage array each comprise a resistive random access memory (RRAM) cell.

14. The method of claim 11, wherein the processing circuit of the first semiconductor substrate comprises a CPU core and an L1 cache, and wherein the storage array of the second semiconductor substrate comprises an L2 cache.

15. The method of claim 11, wherein the storage array comprises a non-volatile word memory array formed of RSM cells, and a non-volatile index array formed of RSM cells, and wherein the method further comprises outputting word data from the word memory array during a data retrieval operation when input request data matches tag data stored in the index array.

16. The method of claim 15, wherein the storage array further comprises a volatile index array formed of volatile memory cells, and wherein the method further comprises accessing the volatile index array to determine a match between said tag data and said input request data, and copying the tag data stored in the non-volatile index array to the volatile index array upon a reinitialization operation.

17. The method of claim 11, wherein the RSM cells are configured as content addressable memory (CAM) cells.

18. The method of claim 11, further comprising a step of writing new word data to a word memory array of the storage array and concurrently writing new tag data associated with the new word data to a corresponding index array of the storage array during a data write operation.

19. The method of claim 11, wherein the storage array of the second semiconductor substrate comprises a cache in a pipeline memory structure of a data storage device with a non-volatile main memory.

20. The method of claim 11, wherein the second semiconductor substrate is standardized to interchangeably affix to a third semiconductor substrate on which is formed a second processing circuit with a hardware configuration different from the processing circuit of the first semiconductor substrate to form a different encapsulated integrated chip package, and wherein the method further comprises affixing a fourth semiconductor substrate nominally identical to the second semiconductor substrate to the third semiconductor substrate to form two respective encapsulated integrated chip packages.