INTEGRATED CIRCUIT RANDOM ACCESS MEMORY CAPABLE OF AUTOMATIC INTERNAL REFRESH OF MEMORY ARRAY
4 Assignments
0 Petitions
Accused Products
Abstract
A dynamic random access memory integrated circuit and method includes internal refresh control and an array configured to receive read and write access requests having priority over pending refresh requests, wherein refresh requests are queueable and retired on clock cycles not requiring an access of the array and complete in one clock cycle. No on-board cache memory is required. A method includes: determining within the circuit when one of the banks of the array requires a refresh, prioritizing read and write access requests over pending refresh requests, read access requests initiating an access to the array without determining whether data is available from outside the array, and retiring within a clock cycle one pending refresh request to a bank when that bank has pending refresh requests and does not also require an access of the array on that clock cycle.
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Citations
35 Claims
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1-20. -20. (canceled)
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21. A method, comprising:
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performing, by a refresh control circuit, an access operation on a first bank of a plurality of memory banks in a memory array; and retiring, by the refresh control circuit and substantially simultaneously with said performing an access operation on a first bank, a pending refresh request for a second memory bank of the plurality of memory banks. - View Dependent Claims (22, 23, 24, 25, 26)
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27. A memory device, comprising:
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first circuitry configured to queue pending refresh requests for a plurality of memory banks; and second circuitry coupled to the first circuitry and configured to set a refresh flag in response to a determination that a number of queued pending refresh requests for a memory bank of the plurality of memory banks exceeds a predetermined number. - View Dependent Claims (28, 29)
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30. A system, comprising:
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a memory array having a plurality of memory banks; and a refresh control circuit coupled to the memory array and configured to; perform an access operation on a first bank of the plurality of memory banks; and retire, substantially simultaneously with a performance of the access operation, a pending refresh request for a second memory bank of the plurality of memory banks. - View Dependent Claims (31, 32, 33, 34, 35)
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Specification