TRANSLATION LAYER IN A SOLID STATE STORAGE DEVICE

• US 20100095084A1
• Filed: 10/13/2008
• Published: 04/15/2010
• Est. Priority Date: 10/13/2008
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Manning, Troy
• Granted Patent: US 8,838,876 B2
• Time in Patent Office: Days
• US Class Current: 711/206
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0292 using tables or multilevel address translation means G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10
• CPC Class Codes: G06F 2212/1044 Space efficiency improvement
• CPC Class Codes: G06F 2212/1048 Scalability
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G11C 16/102 External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Solid state storage devices and methods for flash translation layers are disclosed. In one such translation layer, a sector indication is translated to a memory location by a parallel unit look-up table is populated by memory device enumeration at initialization. Each table entry is comprised of communication channel, chip enable, logical unit, and plane for each operating memory device found. When the sector indication is received, a modulo function operates on entries of the look-up table in order to determine the memory location associated with the sector indication.

Claims

1. A method for translating between a sector indication and a memory location in a solid state device, the method comprising:

enumerating memory devices and each memory device location that comprise the solid state device;

determining a target memory device of the memory devices in response to the sector indication and the memory device locations; and

determining a target data block and the memory location in the target memory device in response to determining the target memory device and a memory density of the target memory device.

2. The method of claim 1 and further including receiving the sector indication from a host computer system.

3. The method of claim 1 wherein enumerating the memory devices and the memory device location comprises determining a communication channel, chip enable, logical unit, and plane for each of the memory devices.

4. The method of claim 1 wherein enumerating the memory devices is performed on initialization of the solid state device.

5. The method of claim 1 and further comprising generating a table of the memory devices and the memory device locations.

6. The method of claim 1 wherein determining the memory density comprises one of multilevel cells or single level cells.

7. A method for translating between a sector indication and a memory location in a solid state drive, the method comprising:

receiving the sector indication;

surveying the solid state drive for memory devices and each memory device location characteristics;

populating a memory device table by memory device enumeration with respective memory device characteristics;

determining a target memory device of the memory devices in response to the sector indication and the memory device table;

generating a data block look-up table comprising indications of which sector indications are stored in the target memory device; and

determining, in response to the data block look-up table, a target memory block and target position in the memory block that stores data for the sector indication.

8. The method of claim 7 wherein the sector indication is a sector number of a hard disk drive.

9. The method of claim 7 wherein surveying the solid state drive comprises determining a communication channel, a chip enable, a logical unit, and a plane for each memory device.

10. The method of claim 9 wherein populating the memory device table comprises assigning a unique identifier to each memory device.

11. The method of claim 7 wherein each memory device table entry is comprised of communication channel information, chip enable information, logical unit information, memory device plane information, and memory device status information.

12. The method of claim 11 wherein the memory device table entry is comprised of two bytes of information.

13. The method of claim 9 wherein the memory device table is populated sequentially for each memory device such that the communication channels have highest priority in the table and the planes have lowest priority in the table.

14. A flash translation layer method for translating between a logical block address (LBA) and a memory location in a solid state drive, the method comprising:

receiving the logical block address from a host system;

surveying the solid state drive during initialization of the solid state drive to find a plurality of parallel units and their location characteristics;

generating a parallel unit look-up table by memory device enumeration wherein the parallel unit look-up table comprises location characteristics associated with each parallel unit;

determining a parallel unit associated with the logical block address in response to a modulo function of the logical block address and a quantity of the plurality of parallel units; and

generating, in response to the modulo function, a data block look-up table that indicates which memory block of the target parallel unit comprises the logical block address.

15. The method of claim 14 wherein the modulo function comprises (Q,R) MOD(LBA>

>

(j=3),N) wherein Q is a quotient, R is a remainder, N is a number of parallel units in the parallel unit look-up table, and j=2^j sectors per page.

16. The method of claim 15 wherein the parallel unit look-up table is indexed by R to determine the location characteristics associated with the R parallel unit.

17. The method of claim 15 wherein the data block look-up table is generated by (R*BlocksPerPU)+(Q>

>

k) where BlocksPerPU are a number of memory blocks in each parallel unit and k is indicative of a memory a number of pages per memory block.

18. The method of claim 17 wherein k=6 for 64 pages per block and k=7 for 128 pages per block.

19. A solid state memory device comprising:

at least one memory array;

a controller coupled to the at least one memory array over at least one communication channel, the controller configured to translate between a disk drive sector indication and a memory location in response to enumeration of the at least one memory array and each memory array location, determination of a target memory array of the at least one memory array in response to the sector indication and the memory array locations, and determination of a target data block and the memory location in the target memory array in response to determining the target memory array and a memory density of the target memory array.

20. The solid state memory device of claim 19 wherein a plurality of memory arrays are coupled to a first communication channel of a plurality of communication channels and each of the plurality of communication channels is coupled to the controller.

21. The solid state memory device of claim 19 wherein the controller is further configured to generate a memory array look-up table that enumerates a communication channel for each memory array, a chip enable for each memory array, a logical unit for each memory array, and a plane for each memory array.

22. The solid state memory device of claim 21 wherein the controller is configured to generate the memory array look-up table in order of communication channel, chip enable, logical unit, and plane.

23. The solid state memory device of claim 19 wherein the memory array is organized in a NAND architecture.

24. The solid state memory device of claim 19 wherein the controller is further configured to generate a data block look-up table that indicates the memory location in the at least one memory array in response to execution of a modulo function.

25. The solid state memory device of claim 19 wherein the memory array is comprised of floating gate memory cells arranged in columns of series strings and rows of word lines.

26. The solid state memory device of claim 25 wherein the floating gate memory cells can be programmed as single level cells or multiple level cells.

27. The solid state memory device of claim 19 and further comprising a plurality of communication channels, each communication channel coupled to a plurality of NAND packages.