RECONFIGURABLE ELEMENTS
First Claim
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1. A data processing chip comprising:
- a plurality of dice, a first of the dice comprising a plurality of processor units and at least one second of the dice comprising at least one data storage memory device, the first and second dice being arranged such that, for each of at least a subset of said processor units provided in a first layer, a dedicated memory storage device is provided in a second layer.
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Abstract
A cell element field for data processing having function cells for execution of algebraic and/or logic functions and memory cells for receiving, storing and/or outputting information is described. A control connection may lead from the function cells to the memory cells.
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Citations
38 Claims
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1. A data processing chip comprising:
a plurality of dice, a first of the dice comprising a plurality of processor units and at least one second of the dice comprising at least one data storage memory device, the first and second dice being arranged such that, for each of at least a subset of said processor units provided in a first layer, a dedicated memory storage device is provided in a second layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A system comprising:
a plurality of chips in a stacked arrangement, at least one of the chips having a power dissipation higher than a power dissipation of at least one other of the chips, wherein said chips are stacked such that said at least one of the chips is arranged at an outer layer of the stack arrangement. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28)
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29. A multi-processor device comprising
a plurality of processor cores; -
a plurality of memory elements; and an interconnection network for interconnecting the memory elements and processor cores; wherein; the memory elements are operable as cache; a given memory element can be connected to a processor core selectable and changeable at runtime via the interconnection network; and the memory elements have a port for connecting to higher level memory so that data can be moved, via said port, into external memory out of said memory elements and from said external memory into said memory elements. - View Dependent Claims (30, 31, 32, 33, 34, 35)
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36. A multi-core processor device comprising:
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multiple processor cores; and an interconnection for communication of data; wherein; a plurality of said multiple processor cores is implemented as a first physical layer on a die; the interconnection structure is implemented as a separate physical layer on a second die; and the first and second dice are arranged in a stacked manner. - View Dependent Claims (37, 38)
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Specification