BOOT ALGORITHM

• US 20100095106A1
• Filed: 10/15/2009
• Published: 04/15/2010
• Est. Priority Date: 10/15/2008
• Status: Active Grant

• Current Assignee: Icera Inc. (NVIDIA Corporation)
• Original Assignee: Icera Inc. (NVIDIA Corporation)
• Inventors: Guasch, Philippe, Alexander, Alan
• Granted Patent: US 8,285,979 B2
• Time in Patent Office: Days
• US Class Current: 713/2
• CPC Class Codes: G06F 9/4408 Boot device selection

Abstract

A method, chip and computer program product for booting from a secondary boot source. In one embodiment, the method includes: (1) retrieving primary boot code from an on-chip primary boot source on the same chip as a processor, the primary boot code comprising at least a boot discovery algorithm for determining the location of an external secondary boot source external to said chip, (2) executing the primary boot code on the processor, including the boot discovery algorithm, thus operating the processor to check each of a plurality of locations to determine the location of the external secondary boot source, (3) retrieving the secondary boot code from the determined location and (4) continuing the booting of the processor by executing the secondary boot code on the processor.

Claims

1. A method of booting a processor of an integrated circuit chip, the method comprising:

retrieving primary boot code from an on-chip primary boot source on the same chip as said processor, the primary boot code comprising at least a boot discovery algorithm for determining the location of an external secondary boot source external to said chip;

executing the primary boot code on said processor, including the boot discovery algorithm, thus operating the processor to check each of a plurality of locations to determine the location of the external secondary boot source;

retrieving the secondary boot code from the determined location; and

continuing the booting of the processor by executing said secondary boot code on the processor.

2. The method according to claim 1, comprising indicating to the processor a selection between a discovery mode in which the secondary boot source is determined using said boot discovery algorithm and a fuse mode in which the location of the secondary boot source is determined by reference to one or more fuse latches.

3. The method according to claim 1, wherein the checking of the external locations is in a predetermined order.

4. The method according claim 1, wherein the checking comprises checking each of said locations to determine whether an external device is connected at that location.

5. The method according to claim 1, wherein the checking comprises checking one or more memory addresses of each of said locations for an indicator indicating the presence of secondary boot code.

6. The method of claim 5, wherein the checking comprises copying data from each of said locations onto an on-chip, randomly accessible memory and checking said addresses using the copied data.

7. The method of claim 1, wherein said retrieval of the secondary boot code comprises copying the secondary boot code from the determined location onto an on-chip, randomly accessible memory and fetching the secondary boot code from the on-chip, randomly accessible memory to the processor.

8. The method according to claim 1, wherein at least one of said locations comprises one of:

a memory interface for connecting to an external memory, and a serial link for connecting to another device.

9. The method according to claim 1, wherein the primary boot source is a ROM.

10. The method according to claim 1, wherein the secondary boot code comprises code for at least partially configuring the processor for communication over a wireless cellular network, such that said execution of the secondary boot code by the processor comprises at least partially configuring the processor for communication over the wireless cellular network.

11. An integrated circuit chip comprising:

an on-chip storage means being a primary boot source storing primary boot code;

a plurality of input locations each being a potential location of an external secondary boot source storing secondary boot code; and

a processor operatively coupled to the primary boot source and to the plurality of input locations;

wherein the processor is configured to, upon booting, automatically retrieve and execute the primary boot code from the primary boot source; and

the primary boot code comprises at least a boot discovery algorithm for determining the location of an external secondary boot source external to said chip, the algorithm being configured so as when executed to operate the processor to check each of said locations to determine the location of the external secondary boot source, retrieve the secondary boot code from the determined location, and continue the booting by executing the secondary boot code.

12. The circuit of claim 11, comprising one or more fuse latches operatively coupled to the processor and storing an indication to the processor, wherein the primary boot code is programmed to refer to the one or more fuse latches to select whether to operate in a discovery mode whereby the secondary boot source is determined using said boot discovery algorithm and a fuse mode in whereby the location of the secondary boot source is determined by reference to one or more fuse latches.

13. The circuit of claim 11, wherein the boot discovery algorithm is configured to check the external locations is in a predetermined order.

14. The circuit of claim 11, wherein the boot discovery algorithm is configured to check each of said locations to determine whether an external device is connected at that location.

15. The circuit of claim 11, wherein the boot discovery algorithm is configured to check one or more memory addresses of each of said locations for an indicator indicating the presence of secondary boot code.

16. The circuit of claim 15, wherein the boot discovery algorithm is configured to copy data from each of said locations onto an on-chip, randomly accessible memory and check said addresses using the copied data.

17. The circuit of claim 11, wherein the boot discovery algorithm is configured to retrieve the secondary boot code by operating the processor to copy the secondary boot code from the determined location onto an on-chip, randomly accessible memory and fetch the secondary boot code from the on-chip, randomly accessible memory to the processor.

18. The circuit of claim 11, wherein at least one of said locations comprises one of:

a memory interface for connecting to an external memory, and a serial link for connecting to another device.

19. The circuit of claim 11, wherein the primary boot source is a ROM.

20. The circuit of claim 11, wherein the secondary boot code comprises code for at least partially configuring the processor for communication over a wireless cellular network, such that the execution of the secondary boot code by the processor comprises at least partially configuring the processor for communication over the wireless cellular network.

21. A computer program product embodied on a computer-readable medium and comprising code which when executed on a processor performs the steps of:

beginning booting of the processor from a primary boot source comprising a boot discovery algorithm, thus operating the processor to check each of a plurality of locations to determine the location of the external secondary boot source;

retrieving the secondary boot code from the determined location; and

continuing the booting of the processor by executing said secondary boot code on the processor.

22. A user equipment comprising a wireless transceiver and an integrated circuit chip, the chip comprising:

an on-chip storage means being a primary boot source storing primary boot code;

a plurality of input locations each being a potential location of an external secondary boot source storing secondary boot code; and

an operatively coupled to the primary boot source and to the plurality of input locations;

wherein the processor is configured to, upon booting, automatically retrieve and execute the primary boot code from the primary boot source; and

the primary boot code comprises at least a boot discovery algorithm for determining the location of an external secondary boot source external to said chip, the algorithm being configured so as when executed to operate the processor to check each of said locations to determine the location of the external secondary boot source, retrieve the secondary boot code from the determined location, and continue the booting by executing the secondary boot code in order to at least partially configure the processor for communication over a wireless cellular network via said wireless transceiver.