THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME

• US 20100096631A1
• Filed: 04/14/2009
• Published: 04/22/2010
• Est. Priority Date: 04/18/2008
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: EGI, Yuji, DAIRIKI, Koji, MIYAIRI, Hidekazu, JINBO, Yasuhiro, ISA, Toshiyuki
• Granted Patent: US 8,138,032 B2
• Time in Patent Office: Days
• US Class Current: 257/57
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78669 with inverted-type structure, e.g. with bottom gate
• CPC Class Codes: H01L 29/78678 with inverted-type structure, e.g. with bottom gate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A thin film transistor includes, over a substrate having an insulating surface, a gate insulating layer covering a gate electrode; a semiconductor layer which includes a plurality of crystalline regions in an amorphous structure and which forms a channel formation region, in contact with the gate insulating layer; a semiconductor layer including an impurity element imparting one conductivity type, which forms source and drain regions; and a buffer layer including an amorphous semiconductor between the semiconductor layer and the semiconductor layer including an impurity element imparting one conductivity type. The crystalline regions have an inverted conical or inverted pyramidal crystal particle which grows approximately radially in a direction in which the semiconductor layer is deposited, from a position away from an interface between the gate insulating layer and the semiconductor layer.

Claims

1. A method for manufacturing a thin film transistor comprising the steps of:

forming a gate electrode over a substrate having an insulating surface;

forming a gate insulating layer over the gate electrode;

forming a semiconductor layer over the gate insulating layer;

forming a buffer layer comprising an amorphous semiconductor, over the semiconductor layer;

forming source and drain regions including an impurity element imparting one conductivity type over the buffer layer; and

forming source and drain electrodes over the source and drain regions, respectively,

wherein the step of the formation of the semiconductor layer includes;

introducing a gas, in which a semiconductor source gas and a diluent gas are mixed, into a reaction chamber;

generating glow discharge plasma in the reaction chamber;

depositing the semiconductor layer to allow the semiconductor layer to include an impurity element which disturbs generation of crystal nuclei in the semiconductor layer; and

generating the crystal nuclei after the semiconductor layer is deposited to a thickness of greater than or equal to 5 nm and less than or equal to 20 nm,

wherein the semiconductor layer comprises a plurality of crystalline regions in an amorphous structure.

2. The method for manufacturing a thin film transistor according to claim 1, further comprising the steps of:

introducing a gas including the impurity element which disturbs generation of the crystal nuclei before the semiconductor source gas and the diluent gas are introduced into the reaction chamber so that the impurity element remains in the reaction chamber; and

exhausting the gas including the impurity element from the reaction chamber.

3. The method for manufacturing a thin film transistor according to claim 1,

wherein the gate insulating layer includes the impurity element which disturbs generation of the crystal nuclei.

4. The method for manufacturing a thin film transistor according to claim 1, further comprising a step of forming, over the gate insulating layer, an insulating layer including the impurity element, which disturbs generation of the crystal nuclei, before the semiconductor layer is formed.

5. The method for manufacturing a thin film transistor according to claim 1,

wherein the semiconductor source gas is a silicon hydride gas, a silicon fluoride gas, or a silicon chloride gas and the diluent gas is a hydrogen gas.

6. The method for manufacturing a thin film transistor according to claim 1,

wherein the impurity element which disturbs generation of the crystal nuclei is nitrogen.

7. A method for manufacturing a thin film transistor comprising the steps of:

forming a gate electrode over a substrate having an insulating surface;

forming a gate insulating layer over the gate electrode;

forming a first semiconductor layer over the gate insulating layer;

forming a buffer layer comprising an amorphous semiconductor, over the first semiconductor layer;

forming a second semiconductor layer including an impurity element imparting one conductivity type over the buffer layer;

forming source and drain electrodes over the second semiconductor layer;

removing part of the first semiconductor layer and part of the second semiconductor layer which are not covered with the source and drain electrodes by dry etching; and

performing plasma treatment on a surface of the first semiconductor layer which is exposed by the removing,

wherein the step of the formation of the first semiconductor layer includes;

introducing a silicon hydride gas, a silicon fluoride gas, or a silicon chloride gas, and a hydrogen gas into a reaction chamber;

generating glow discharge plasma in the reaction chamber; and

depositing the first semiconductor layer to allow the first semiconductor layer to include an impurity element which disturbs generation of crystal nuclei at an early stage of the deposition,

wherein the first semiconductor layer comprises a plurality of crystalline regions in an amorphous structure.

8. The method for manufacturing a thin film transistor according to claim 7, further comprising the steps of

introducing a gas including the impurity element which disturbs generation of the crystal nuclei into the reaction chamber before the silicon hydride gas, the silicon fluoride gas, or the silicon chloride gas, and the hydrogen gas are introduced into the reaction chamber so that the impurity element remains in the reaction chamber;

and

exhausting the gas including the impurity element from the reaction chamber.

9. The method for manufacturing a thin film transistor according to claim 7,

wherein the gate insulating layer includes the impurity element which disturbs generation of the crystal nuclei.

10. The method for manufacturing a thin film transistor according to claim 7, further comprising a step of forming, over the gate insulating layer, an insulating layer including the impurity element, which disturbs generation of the crystal nuclei, before the first semiconductor layer is formed.

11. The method for manufacturing a thin film transistor according to claim 7,

wherein the impurity element which disturbs generation of the crystal nuclei is nitrogen.

12. A thin film transistor comprising:

a gate electrode over a substrate having an insulating surface;

a gate insulating layer over the gate electrode;

a first semiconductor layer on and in contact with the gate insulating layer wherein the first semiconductor layer exists in a state that a plurality of crystalline regions are dispersed in an amorphous structure;

a second semiconductor layer comprising an amorphous structure over the first semiconductor layer; and

source and drain regions over the second semiconductor layer, the source and drain regions comprising an impurity element imparting one conductivity type,

wherein the crystalline regions have an inverted conical or inverted pyramidal crystal particle whose vertex is located on a side of the gate insulating layer.

13. The thin film transistor according to claim 12,

wherein in the first semiconductor layer, a concentration of oxygen which is measured by secondary ion mass spectrometry is less than or equal to 5×

10¹⁸ cm<sup>−

3</sup> and a concentration of nitrogen which is measured by secondary ion mass spectrometry ranges from 1×

10²⁰ cm<sup>−

3</sup> to 1×

10²¹ cm<sup>−

3</sup>.

14. The thin film transistor according to claim 13,

wherein in the first semiconductor layer, a peak concentration of nitrogen which is measured by secondary ion mass spectrometry ranges from 3×

10²⁰ cm<sup>−

3</sup> to 1×

10²¹ cm<sup>−

3</sup> and the concentration of nitrogen is decreased as a distance from the gate insulating layer is increased.

15. The thin film transistor according to claim 13,

wherein the vertex exists in a region where the concentration of nitrogen in the first semiconductor layer is greater than or equal to 1×

10²⁰ cm<sup>−

3</sup> and less than or equal to 3×

10²⁰ cm<sup>−

3</sup>.

16. The thin film transistor according to claim 12,

wherein the inverted conical or inverted pyramidal crystal particle is a single crystal.

17. The thin film transistor according to claim 12,

wherein the crystal particle includes a twin crystal.