MEMORY CELL ARRAY COMPRISING WIGGLED BIT LINES
First Claim
1. An integrated circuit including a memory cell array comprising:
- transistors arranged along parallel continuous active area lines;
bitlines arranged such that individual ones of the bitlines intersect a plurality of the continuous active area lines to form bitline-contacts, respectively, the bitlines being formed as wiggled lines; and
wordlines arranged so that individual ones of the wordlines intersect a plurality of the continuous active area lines, and individual ones of the wordlines intersect a plurality of the bitlines, wherein neighboring bitline-contacts, each of which is connected to one of the continuous active area lines, are connected with different bitlines.
3 Assignments
0 Petitions
Accused Products
Abstract
An integrated circuit including a memory cell array comprises transistors being arranged along parallel active area lines, bitlines, the bitlines being arranged so that an individual one intersects a plurality of the active area lines to form bitline-contacts, respectively, the bitlines being formed as wiggled lines, wordlines being arranged so that an individual one of the wordlines intersects a plurality of the active area lines, and an individual one of the wordlines intersects a plurality of the bitlines, wherein neighboring bitline-contacts, each of which is connected to one of the active area lines, are connected with different bitlines.
20 Citations
22 Claims
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1. An integrated circuit including a memory cell array comprising:
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transistors arranged along parallel continuous active area lines; bitlines arranged such that individual ones of the bitlines intersect a plurality of the continuous active area lines to form bitline-contacts, respectively, the bitlines being formed as wiggled lines; and wordlines arranged so that individual ones of the wordlines intersect a plurality of the continuous active area lines, and individual ones of the wordlines intersect a plurality of the bitlines, wherein neighboring bitline-contacts, each of which is connected to one of the continuous active area lines, are connected with different bitlines. - View Dependent Claims (3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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2. (canceled)
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13. An integrated circuit including a memory cell array comprising:
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bitlines formed as wiggled lines, the bitlines generally extending along a first direction; wordlines running along a second direction; continuous active area lines, transistors being formed in the active area lines, the active area lines extending in a direction that is slanted with respect to the first and second directions; and bitline contacts disposed in regions generally defined by an intersection of a bitline and a corresponding continuous active area line; wherein neighboring bitline contacts that are shifted along a direction that is slanted with respect to the first and second directions, respectively, and that are disposed in regions corresponding to a same continuous active area line, are connected with neighboring bitlines. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22)
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14. (canceled)
Specification