SEMICONDUCTOR DEVICE

• US 20100096692A1
• Filed: 08/06/2009
• Published: 04/22/2010
• Est. Priority Date: 10/16/2008
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: HATANO, Nana, OHTA, Hiroshi, WATANABE, Miho, ONO, Syotaro, SAITO, Wataru
• Granted Patent: US 7,755,138 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device of the invention includes: a super junction structure of an n-type pillar layer and a p-type pillar layer; a base layer provided on the p-type pillar layer; a source layer selectively provided on a surface of the base layer; a gate insulating film provided on a portion being in contact with the base layer, a portion being in contact with the source layer and a portion being in contact with the n-type pillar layer on a portion of a junction between the n-type pillar layer and the p-type pillar layer; a control electrode provided opposed to the base layer, the source layer and the n-type pillar layer through the gate insulating film; and a source electrode electrically connected to the base layer, the source layer and the n-type layer. The source electrode is contact with the surface of the n-type pillar layer located between the control electrodes to form a Schottky junction.

Claims

1. A semiconductor device comprising:

a first semiconductor layer of a first conductivity type;

a second semiconductor layer of a first conductivity type provided on a major surface of the first semiconductor layer;

a third semiconductor layer of a second conductivity type provided above the major surface of the first semiconductor layer adjacent to the second semiconductor layer, and forming a periodical arrangement structure in conjunction with the second semiconductor layer in a lateral direction generally parallel to the major surface of the first semiconductor layer;

a fourth semiconductor layer of a second conductivity type provided on the third semiconductor layer;

a fifth semiconductor layer of a first conductivity type selectively provided on a surface of the fourth semiconductor layer;

a first main electrode electrically connected to the first semiconductor layer;

a gate insulating film provided on a portion being in contact with the fourth semiconductor layer, a portion being in contact with the fifth semiconductor layer and a portion being in contact with the second semiconductor layer;

a control electrode provided opposed to the fourth semiconductor layer, the fifth semiconductor layer and the second semiconductor layer via the gate insulating film; and

a second main electrode electrically connected to the fourth semiconductor layer, the fifth semiconductor layer and the second semiconductor layer,

the second main electrode being in contact with a surface of the second semiconductor layer located between the control electrodes to form a Schottky junction.

2. The device according to claim 1, wherein the control electrode is provided above a junction interface between the second semiconductor layer and the third semiconductor layer via the gate insulating film.

3. The device according to claim 1, wherein the gate insulating film and the control electrode are provided in a trench formed in contact with the fourth semiconductor layer, the fifth semiconductor layer and the second semiconductor layer.

4. The device according to claim 3, wherein the second main electrode is in contact with the surface of the second semiconductor layer with a width narrower than a depth of the trench.

5. The device according to claim 3, wherein a sixth semiconductor layer of a second conductivity type is selectively provided on the surface of the second semiconductor layer.

6. The device according to claim 5, wherein the sixth semiconductor layer is provided at a center of the surface of the second semiconductor layer and not in contact with the gate insulating film.

7. The device according to claim 1, wherein

the gate insulating film and the control electrode are provided in a trench formed in contact with the fourth semiconductor layer, the fifth semiconductor layer and the second semiconductor layer,

a sixth semiconductor layer of a second conductivity is selectively provided on the surface of the second semiconductor layer, and

the trench and the sixth semiconductor layer are formed in a striped configuration orthogonal to each other.

8. The device according to claim 1, wherein

the gate insulating film and the control electrode are provided in a trench formed in contact with the fourth semiconductor layer, the fifth semiconductor layer and the second semiconductor layer, and

a bottom depth of the fourth semiconductor layer is larger than a bottom depth of the trench.

9. The device according to claim 8, wherein a sixth semiconductor layer of a second conductivity type is selectively provided on the surface of the second semiconductor layer.

10. The device according to claim 1, wherein

the gate insulating film and the control electrode are provided in a first trench formed in contact with the fourth semiconductor layer, the fifth semiconductor layer and the second semiconductor layer, and

a second trench is provided on a superficial portion of the second semiconductor layer.

11. The device according to claim 10, wherein the same material as the gate insulating film and the control electrode is embedded inside the second trench.

12. The device according to claim. 10, wherein

a sixth semiconductor layer of a second conductivity type is provided on a bottom of the second trench, and

the second main electrode is embedded inside the second trench.

13. The device according to claim 1, wherein the gate insulating film and the control electrode include a planar gate structure.

14. The device according to claim 13, wherein a sixth semiconductor layer of a second conductivity type is selectively provided on the surface of the second semiconductor layer.

15. The device according to claim 1, wherein a width of the third semiconductor layer is narrower than a width of the second semiconductor layer.

16. The device according to claim 15, wherein

a lateral period of the third semiconductor layer is 1/2 times of a lateral period of the fourth semiconductor layer, and

the third semiconductor layer not in contact with the fourth semiconductor layer is in contact with the second main electrode.

17. The device according to claim 16, wherein a seventh semiconductor layer of a second conductivity type is provided on a surface of the third semiconductor layer in contact with the second main electrode.

18. The device according to claim 17, wherein the seventh semiconductor layer has a higher second conductivity type impurity concentration than the third semiconductor layer.

19. The device according to claim 1, wherein a transistor including the fourth semiconductor layer and the fifth semiconductor layer and a Schottky barrier diode including the Schottky junction are connected in parallel between the first main electrode and the second main electrode.

20. The device according to claim 19, wherein one of the second semiconductor layer in a unit cell of the periodical arrangement structure made of the second semiconductor layer and the third semiconductor layer is shared between the transistor and the Schottky barrier diode as a drift layer.