SEMICONDUCTOR DEVICE WITH VERTICAL GATE AND METHOD FOR FABRICATING THE SAME

• US 20100096693A1
• Filed: 06/29/2009
• Published: 04/22/2010
• Est. Priority Date: 10/17/2008
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Hong, Ki-Ro
• Granted Patent: US 8,120,103 B2
• Time in Patent Office: Days
• US Class Current: 257/331
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/482 Bit lines

Abstract

A semiconductor device includes a substrate; a plurality of active pillars formed over the substrate; bulb-type trenches, each of the bulb-type trenches formed inside the substrate between the active pillars; buried bit lines, each of the buried bit lines being formed on a sidewall of a respective one of the bulb-type trenches; and vertical gates, each of the vertical gates being formed to surround a sidewall of a respective one of the active pillars.

Claims

1. A semiconductor device, comprising:

a substrate;

a plurality of active pillars formed over the substrate;

bulb-type trenches, each of the bulb-type trenches formed inside the substrate between the active pillars;

buried bit lines, each of the buried bit lines being formed on a sidewall of a respective one of the bulb-type trenches; and

vertical gates, each of the vertical gates being formed to surround a sidewall of a respective one of the active pillars.

2. The semiconductor device of claim 1, wherein the plurality of active pillars are arrayed with a first space and a second space, the second space being narrower than the first space.

3. The semiconductor device of claim 2, wherein the plurality of active pillars include a number of active pillar array pairs wherein the active pillar array pairs are arranged with the second space therebetween and active pillar arrays in each active pillar array pair are arranged with the first space therebetween, the second space being narrower than the first space.

4. The semiconductor device of claim 3, wherein the bulb-type trenches are formed inside the substrate beneath the first space.

5. The semiconductor device of claim 1, further comprising:

a trench under each of the bulb-type trenches.

6. The semiconductor device of claim 1, wherein the active pillars include a neck-free structure.

7. The semiconductor device of claim 1, wherein the buried bit lines include a metal layer or a metal nitride layer.

8. The semiconductor device of claim 7, wherein the buried bit lines include a tungsten (W) layer or a titanium nitride (TiN) layer.

9. A method for fabricating a semiconductor device, comprising:

forming a plurality of preliminary active pillars arrayed with a first space and a second space by etching a substrate, the second space being narrower than the first space;

forming bulb-type trenches by etching the substrate beneath the first space;

forming buried bit lines, each of the buried bit lines being formed on each sidewall of a respective one of the bulb-type trenches;

forming a plurality of active pillars by etching the preliminary active pillars; and

forming vertical gates, each of the vertical gate surrounding a sidewall of a respective one of the active pillars.

10. The method of claim 9, wherein the forming of the bulb-type trenches includes:

forming a spacer layer to gap-fill the second space between the preliminary active pillars;

performing an etch-back on the spacer layer; and

forming the bulb-type trenches by etching the substrate with the spacer layer used as an etch barrier.

11. The method of claim 10, wherein the spacer layer gap-fills the second space and covers sidewalls and an upper portion of the preliminary active pillars neighboring with the first space therebetween.

12. The method of claim 10, wherein the spacer layer includes an oxide layer.

13. The method of claim 9, wherein the forming of the buried bit lines includes:

depositing a conductive layer which gap-fills the bulb-type trenches over a substrate structure; and

performing an etch-back onto the conductive layer.

14. The method of claim 13, wherein the conductive layer includes a metal layer or a metal nitride layer.

15. The method of claim 14, wherein the conductive layer includes a tungsten (W) layer or a titanium nitride (TiN) layer.

16. The method of claim 9, wherein the plurality of preliminary active pillars are formed in a line-space type by using a hard mask layer as an etch barrier.

17. The method of claim 16, wherein the hard mask layer includes a nitride layer, an oxide layer, and an amorphous carbon layer stacked sequentially.

18. The method of claim 9, further comprising, after the forming of the buried bit lines, forming trenches by further etching a bottom portion of each of the bulb-type trenches.

19. The method of claim 9, wherein the preliminary active pillars are formed in a line shape, and the active pillars are formed through an etch process performed by using a line-shaped photoresist pattern perpendicularly crossing the preliminary active pillars.

20. The method of claim 19, wherein each of the active pillars is formed in a straight line shape without a neck.