SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

• US 20100096749A1
• Filed: 03/17/2009
• Published: 04/22/2010
• Est. Priority Date: 10/21/2008
• Status: Active Grant

• Current Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Original Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Inventors: LEE, Jae-Kwang, KWEON, Young-Do, KIM, Woon-Chun, YIM, Soon-Gyu
• Granted Patent: US 8,159,071 B2
• Time in Patent Office: Days
• US Class Current: 257/737
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13024 the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/525 with adaptable interconnections
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/10 Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/14 of a plurality of bump connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/014 : Solder alloys

Abstract

Disclosed are a semiconductor package and a manufacturing method thereof. The semiconductor package can include a semiconductor substrate, having one surface on which a conductive pad is formed; an insulating layer, being formed on one surface of the semiconductor substrate; a metal post, penetrating through the conductive pad, the semiconductor substrate, and the insulating layer; and an outer-layer circuit, being electrically connected to the metal post. With the present invention, it can become unnecessary to form an additional via for electrically connecting both surfaces of the semiconductor substrate, thereby simplifying the manufacturing process, reducing the manufacturing cost, and improving the coupling reliability.

Claims

1. A semiconductor package comprising:

a semiconductor substrate, of which one surface is formed with a conductive pad;

an insulating layer, being formed on one surface of the semiconductor substrate;

a metal post, penetrating through the conductive pad, the semiconductor substrate and the insulating layer; and

an outer-layer circuit, being electrically connected to the metal post.

2. The semiconductor package of claim 1, further comprising a solder bump, being formed on the outer-layer circuit.

3. A method of manufacturing a semiconductor package, the method comprising:

providing a semiconductor substrate, of which one surface is formed with a conductive pad;

forming a hole on one surface of the semiconductor substrate such that the hole penetrates through the conductive pad;

forming an insulating layer on one surface of the semiconductor substrate and a metal post on the hole to allow the metal post to penetrate through the insulating layer; and

forming an outer-layer circuit to be electrically connected to the metal post.

4. The method of claim 3, wherein the forming of the hole is performed such that a depth of the hole is equal to or smaller than a thickness of the semiconductor substrate, and further comprising, prior to the forming of the outer-layer circuit, removing a part of the semiconductor substrate to expose the metal post.

5. The method of claim 3, wherein the forming of the insulating layer and the metal post comprises:

forming the insulating layer on one surface of the semiconductor substrate, an opening being formed on the insulating layer corresponding to a position of the conductive pad; and

forming the metal post by filling a conductive material inside the hole and the opening.

6. The method of claim 3, further comprising, after the forming of the outer-layer circuit, forming a solder bump on the outer-layer circuit.