HVNMOS/HVPMOS switched capacitor charge pump having ideal charge transfer

• US 20100097125A1
• Filed: 11/05/2008
• Published: 04/22/2010
• Est. Priority Date: 10/20/2008
• Status: Active Grant

• Current Assignee: Dialog Semiconductor GmbH (Renesas Electronics Corporation)
• Original Assignee: Dialog Semiconductor GmbH (Renesas Electronics Corporation)
• Inventors: Ji, Cang
• Granted Patent: US 7,843,251 B2
• Time in Patent Office: Days
• US Class Current: 327/536
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: H02M 3/073 Charge pumps of the Schenkel-type
• CPC Class Codes: H02M 3/078 with means for reducing the back bias effect, i.e. the effect which causes the threshold voltage of transistors to increase as more stages are added to the converters

Abstract

An integrated circuit for a charge pump with a charge stage and a pump stage and a single High-Voltage PMOS (HVPMOS) transistor as the main switch for each stage and two times two minimum HVPMOS transistors in series as a bulk switch with fixed bulk connections, where the minimum HVPMOS transistors are smaller sized transistors than the transistors of the main switch. The bulk of the main switch is switched synchronously to the voltage node of the HVPMOS transistor of the main switch to force the bulk voltage (V_B) to be equal or larger than either the source voltage (V_S) or the drain voltage (V_D). Two non-overlapping clock signals are used to trigger the HVPMOS transistors of the charge and pump stage.

Claims

1. A HVNMOS/HVPMOS switched capacitor charge pump, comprising:

a charge stage for charging a first capacitive means and a pump stage for charging a second capacitive means, said pump stage coupled to said charge stage for transferring a charge of said first capacitive means to said second capacitive means, thereby raising the voltage potential of said second capacitive means to above the voltage potential of said first capacitive means,

where a HVPMOS transistor of said charge stage is coupled between a first input of said charge stage and a first terminal of said first capacitive means, and where a HVPMOS transistor of said pump stage is coupled between said first terminal of said first capacitive means and a first terminal of said second capacitive means;

a bulk switch circuit for synchronously switching the bulk of said HVPMOS transistors of said charge stage and said pump stage to the voltage node of said HVPMOS transistors, said bulk switch circuit comprising serially coupled minimum HVPMOS transistors, each said minimum HVPMOS transistor having their drains coupled together, and where a bulk terminal of each of said minimum HVPMOS transistors is coupled to its respective source,

where a first said bulk switch circuit is coupled in parallel to a drain and a bulk terminal of said HVPMOS transistor of said charge stage,

where a second said bulk switch circuit is coupled in parallel to said bulk terminal and a source of said HVPMOS transistor of said charge stage,

where a third said bulk switch circuit is coupled in parallel to a drain and a bulk terminal of said HVPMOS transistor of said pump stage; and

where a fourth said bulk switch circuit is coupled in parallel to said bulk terminal and a source of said HVPMOS transistor of said pump stage.

2. The HVNMOS/HVPMOS switched capacitor charge pump of claim 1, wherein drains of said HVPMOS transistors are extended drain regions.

3. The HVNMOS/HVPMOS switched capacitor charge pump of claim 1, wherein said drains of said minimum HVPMOS transistors are extended drain regions.

4. The HVNMOS/HVPMOS switched capacitor charge pump of claim 1, wherein said drain of said HVPMOS transistor of said charge stage is coupled to said first input of said charge stage and where said source of said HVPMOS transistor of said charge stage is coupled to said first terminal of said first capacitive means.

5. The HVNMOS/HVPMOS switched capacitor charge pump of claim 1, wherein a source and a bulk terminal of an HVNMOS transistor are coupled to a second input of said charge stage and where an extended drain region of said HVNMOS transistor is coupled to said second terminal of said first capacitive means.

6. The HVNMOS/HVPMOS switched capacitor charge pump of claim 1, wherein said drain of said HVPMOS transistor of said pump stage is coupled to said first terminal of said first capacitive means and where said source of said HVPMOS transistor of said pump stage is coupled to said first terminal of said second capacitive means and a first output.

7. The HVNMOS/HVPMOS switched capacitor charge pump of claim 1, wherein an extended drain of a low-side HVPMOS transistor of said pump stage is coupled to said second terminal of said first capacitive means and where a source and a bulk terminal of said low-side HVPMOS transistor of said pump stage are coupled to said second terminal of said second capacitive means and a second output.

8. The HVNMOS/HVPMOS switched capacitor charge pump of claim 1, wherein gates of said first bulk switch, said HVPMOS, and said HVNMOS transistor of said charge stage are clocked by a first signal T1.

9. The HVNMOS/HVPMOS switched capacitor charge pump of claim 8, wherein gates of said second bulk switch are clocked by the inverse of said first signal T1.

10. The HVNMOS/HVPMOS switched capacitor charge pump of claim 1, wherein gates of said third bulk switch, said HVPMOS, and said low-side HVPMOS transistor of said pump stage are clocked by a second signal T2.

11. The HVNMOS/HVPMOS switched capacitor charge pump of claim 10, wherein gates of said fourth bulk switch are clocked by the inverse of said second signal T2.

12. A HVNMOS/HVPMOS switched capacitor charge pump, comprising:

a charge stage for charging a first capacitive means and a pump stage for charging a second capacitive means, said pump stage coupled to said charge stage for transferring a charge of said first capacitive means to said second capacitive means, thereby raising the voltage potential of said second capacitive means to above the voltage potential of said first capacitive means,

where said charge stage comprises a HVPMOS transistor and a HVNMOS transistor, said HVPMOS transistor of said charge stage coupling a first input of said charge stage to a first terminal of said first capacitive means, said HVNMOS transistor of said charge stage coupling a second input of said charge stage to a second terminal of said first capacitive means, where gates of said HVPMOS and HVNMOS transistors of said charge stage when clocked by a first signal T1 cause said first capacitive means to be charged,

where said pump stage comprises a first and a second HVPMOS transistor, said first HVPMOS transistor of said pump stage coupling said first terminal of said first capacitive means to a first terminal of said second capacitive means, said second HVPMOS transistor of said pump stage coupling said second terminal of said first capacitive means to a second terminal of said second capacitive means, where gates of said first and said second HVPMOS transistor of said pump stage when clocked by a second signal T2 cause a charge of said first capacitive means to be transferred to said second capacitive means, and;

a bulk switch circuit for synchronously switching the bulk of said HVPMOS transistors of said charge stage and said pump stage to the voltage node of said HVPMOS transistors, said bulk switch circuit comprising a first and a second serially coupled minimum HVPMOS transistor, each said minimum HVPMOS transistor having a source, a drain, a gate, and a bulk terminal, where said drains of said first and second minimum HVPMOS transistor are coupled together, where said gates of said first and second minimum HVPMOS transistor are coupled together, and where said bulk terminal of each of said first and second minimum HVPMOS transistor is coupled to its respective said source,

where said sources of a first said bulk switch circuit are coupled to said drain and said bulk terminal, respectively, of said HVPMOS transistor of said charge stage,

where said sources of a second said bulk switch circuit are coupled to said bulk terminal and said source, respectively, of said HVPMOS transistor of said charge stage,

where said sources of a third said bulk switch circuit are coupled to said drain and said bulk terminal, respectively, of said first HVPMOS transistor of said pump stage, and

where said sources of a fourth said bulk switch circuit are coupled to said bulk terminal and said source, respectively, of said first HVPMOS transistor of said pump stage.

13. The HVNMOS/HVPMOS switched capacitor charge pump of claim 12, wherein said drains of said HVPMOS transistors and of said HVNMOS transistor are extended drain regions.

14. The HVNMOS/HVPMOS switched capacitor charge pump of claim 12, wherein said drains of said minimum HVPMOS transistors are extended drain regions.

15. The HVNMOS/HVPMOS switched capacitor charge pump of claim 12, wherein said drain of said HVPMOS transistor of said charge stage is coupled to said first input of said charge stage and where said source of said HVPMOS transistor of said charge stage is coupled to said first terminal of said first capacitive means.

16. The HVNMOS/HVPMOS switched capacitor charge pump of claim 12, wherein said source and a bulk terminal of said HVNMOS transistor of said charge stage is coupled to said second input of said charge stage and where said drain of said HVNMOS transistor of said charge stage is coupled to said second terminal of said first capacitive means.

17. The HVNMOS/HVPMOS switched capacitor charge pump of claim 12, wherein said drain of said first HVPMOS transistor of said pump stage is coupled to said first terminal of said first capacitive means and where said source of said first HVPMOS transistor of said pump stage is coupled to said first terminal of said second capacitive means and a first output.

18. The HVNMOS/HVPMOS switched capacitor charge pump of claim 12, wherein said drain of said second HVPMOS transistor of said pump stage is coupled to said second terminal of said first capacitive means and where said source and a bulk terminal of said HVPMOS transistor of said charge stage is coupled to said second terminal of said second capacitive means and a second output.

19. The HVNMOS/HVPMOS switched capacitor charge pump of claim 12, wherein said gates of said second bulk switch are clocked by the inverse of said first signal T1.

20. The HVNMOS/HVPMOS switched capacitor charge pump of claim 12, wherein said gates of said fourth bulk switch are clocked by the inverse of said second signal T2.

21. A method of synchronously switching the bulk of a charge pump, comprising the steps of:

a) providing a charge pump with a charge stage and a pump stage to charge capacitors;

b) providing each of said stages with a main switch comprising a single HVPMOS transistor with an extended drain;

c) coupling a bulk switch each, across the extended drain and source of each HVPMOS transistor;

d) providing each bulk switch with minimum-size HVPMOS transistors, where the sources of two of these minimum-size HVPMOS transistors are coupled, forming a junction;

e) coupling the junction of the sources to the bulk of the HVPMOS transistor;

f) providing a first clocking signal to gate the main switch of the charge stage; and

g) providing a second clocking signal to gate the main switch of the pump stage.