LIQUID CRYSTAL DISPLAY

• US 20100097366A1
• Filed: 04/22/2008
• Published: 04/22/2010
• Est. Priority Date: 04/26/2007
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Nakagawa, Hidetoshi, Yamada, Naoshi, Shimoshikiryoh, Fumikazu, Kitayama, Masae, Tsubata, Toshihide, Irie, Kentaroh
• Granted Patent: US 9,196,206 B2
• Time in Patent Office: Days
• US Class Current: 345/213
• CPC Class Codes: G02F 1/133707 Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes
• CPC Class Codes: G02F 1/134336 Matrix
• CPC Class Codes: G02F 1/134345 Subdivided pixels, e.g. for grey scale or redundancy
• CPC Class Codes: G02F 1/1362 Active matrix addressed cells G02F1/134336, G02F1/134363 take precedence
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 2201/122 having a particular pattern
• CPC Class Codes: G02F 2201/123 pixel
• CPC Class Codes: G09G 2300/0413 Details of dummy pixels or dummy lines in flat panels
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2300/0443 with several sub-pixels for the same colour in a pixel, not specifically used to display gradations G09G3/364 takes precedence
• CPC Class Codes: G09G 2300/0447 for multi-domain technique to improve the viewing angle in a liquid crystal display, such as multi-vertical alignment [MVA]
• CPC Class Codes: G09G 2300/0876 Supplementary capacities in pixels having special driving circuits and electrodes instead of being connected to common electrode or ground; Use of additional capacitively coupled compensation electrodes
• CPC Class Codes: G09G 2310/0224 Details of interlacing
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/06 Details of flat display driving waveforms
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2320/0233 Improving the luminance or brightness uniformity across the screen
• CPC Class Codes: G09G 3/2077 by a combination of two or more gradation control methods
• CPC Class Codes: G09G 3/3614 Control of polarity reversal in general
• CPC Class Codes: G09G 3/3655 Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors
• CPC Class Codes: G09G 3/3666 : with the matrix divided into sections
• CPC Class Codes: G09G 3/3677 : suitable for active matrices only
• CPC Class Codes: G09G 3/3688 : suitable for active matrices only
• CPC Class Codes: G11C 19/00 : Digital stores in which the information is moved stepwise, e.g. shift registers

Abstract

In one embodiment of the present invention, each pixel includes first and second subpixels. CS bus lines connected to the respective storage capacitors of the first and second subpixels are electrically independent of each other. A CS voltage has a waveform that inverts its polarity at least once a frame, which includes a first subframe for sequentially scanning a series of odd rows and a second SF for sequentially scanning even rows that have been skipped during the first SF. A source signal voltage varies so as to have two frames or subframes with mutually opposite polarities. A CS voltage has a waveform that has quite opposite consequences on the effective voltage of a subpixel of a pixel connected to the j^th scan line to be selected during the first subframe and on that of another subpixel of a pixel connected to the (j+1)^th scan line to be selected during the second subframe. In this manner, the deterioration in display quality, which would be caused if either a source line inversion drive or a block inversion drive is applied to a multi-pixel technology, can be minimized.

Claims

1. A liquid crystal display device comprising:

a number of pixels that are arranged in columns and rows to form a matrix pattern, each said pixel including first and second subpixels that are able to exhibit mutually different luminances at least at a certain grayscale;

a plurality of source bus lines, each of which is associated with one of the columns of pixels;

a plurality of gate bus lines, each of which is associated with one of the rows of pixels;

a plurality of TFTs, each of which is associated with one of the first and second subpixels of an associated one of the pixels; and

a plurality of CS bus lines, each of which is associated with either the respective first subpixels or the respective second subpixels of one of the rows of pixels, and

wherein each of the first and second subpixels includes a liquid crystal capacitor and a storage capacitor, and

wherein the CS bus lines connected to the respective storage capacitors of the first and second subpixels are electrically independent of each other, and

wherein the pixels are scanned by supplying gate signal voltages to the respective gate bus lines; and

wherein a CS voltage supplied to each said CS bus line has a waveform, of which the polarity changes at least once a vertical scanning period, and

wherein each said vertical scanning period has multiple vertical scanning sub-periods including a first vertical scanning sub-period for sequentially scanning a series of odd or even rows of pixels and a second vertical scanning sub-period, which is continuous with the first vertical scanning sub-period, for sequentially scanning even or odd rows of pixels that have been skipped during the first vertical scanning sub-period, and

wherein the polarity of a source signal voltage supplied to each said source bus line changes in a predetermined sequence, which includes a series of two vertical scanning periods or sub-periods in which the source signal voltage has mutually opposite polarities, and

wherein the CS voltage has a waveform that alternately performs the function of increasing or decreasing the effective voltage of one of two subpixels, which is associated with a CS bus line supplied with the CS voltage, in each of pixels that are connected to a j^th gate bus line to be selected during the first vertical scanning sub-period, and the function of increasing or decreasing the effective voltage of one of two subpixels, which is associated with a CS bus line supplied with the CS voltage, in each of pixels that are connected to a (j+1)^th gate bus line to be selected during the second vertical scanning sub-period.

2. The liquid crystal display device of claim 1, wherein the sequence of the source signal voltage includes a series of two vertical scanning periods in which the source signal voltage has mutually opposite polarities, the source signal voltage keeping the same polarity through the first and second vertical scanning sub-periods of the same vertical scanning period, and

wherein the CS voltage inverts its polarity an odd number of times since a gate signal voltage supplied to the j^th gate bus line has changed from high into low during the first vertical scanning sub-period and until a gate signal voltage supplied to the (j+1)^th gate bus line changes from high into low during the second vertical scanning sub-period.

3. The liquid crystal display device of claim 1, wherein the sequence of the source signal voltage includes a series of two vertical scanning sub-periods in which the source signal voltage has mutually opposite polarities, the source signal voltage having mutually opposite polarities in the first and second vertical scanning sub-periods of the same vertical scanning period, and

wherein the CS voltage inverts its polarity an even number of times since a gate signal voltage supplied to the j^th gate bus line has changed from high into low during the first vertical scanning sub-period and until a gate signal voltage supplied to the (j+1)^th gate bus line changes from high into low during the second vertical scanning sub-period.

4. The liquid crystal display device of claim 3, wherein the CS voltage inverts its polarity an even number of times, which is at least twice, since the gate signal voltage supplied to the j^th gate bus line has changed from high into low during the first vertical scanning sub-period and until the gate signal voltage supplied to the (j+1)^th gate bus line changes from high into low during the second vertical scanning sub-period, and

wherein once a predetermined voltage has been applied to the (j+1)^th row of pixels, the CS voltage level stays at the center level thereof.

5. The liquid crystal display device of claim 1, wherein every odd or even row of pixels are scanned during the first vertical scanning sub-period and the rest of the odd or even rows of pixels that have not been scanned yet are scanned during the second vertical scanning sub-period.

6. The liquid crystal display device of claim 1, wherein the CS bus lines include at least one CS bus line that is associated in common with two subpixels that belong to two different pixels and that are adjacent to each other in the column direction.

7. The liquid crystal display device of claim 3, wherein the CS voltage has a waveform, a part of which oscillates in a period that is a positive integral number of times as long as one horizontal scanning period, and

wherein each said vertical scanning sub-period is a period for scanning a series of Nsv (=α

/2) odd or even rows of pixels, and

wherein if one period of the CS voltage is represented by M×

H where H is one horizontal scanning period and M is a positive integer, Nsv is a positive integral number of times as large as M/2.

8. The liquid crystal display device of claim 7, wherein each said vertical scanning period includes not only the first and second vertical scanning sub-periods but also third and fourth vertical scanning sub-periods that are continuous with the second and third vertical scanning sub-periods, respectively, and

wherein the third vertical scanning sub-period is a period for sequentially scanning a series of Nsv odd or even rows of pixels, beginning with an odd or even row continuously with the last odd or even row that has been scanned during the second vertical scanning sub-period, while the fourth vertical scanning sub-period is a period for sequentially scanning even or odd rows of pixels that have been skipped during the third vertical scanning sub-period, and

wherein the sequence includes a sequence in which the source signal voltage has different polarities between the first and second vertical scanning sub-periods, the same polarity between the second and third vertical scanning sub-periods, and different polarities again between the third and fourth vertical scanning sub-periods.

9. The liquid crystal display device of claim 7, wherein the CS bus lines include at least one CS bus line that is associated in common with two subpixels that belong to two different pixels and that are adjacent to each other in the column direction, and

wherein if one period of the CS voltage is represented by M×

H where H is one horizontal scanning period and M is a positive integer, Nsv is a positive integral number of times as large as M.

10. The liquid crystal display device of claim 7, wherein Nsv×

H (where H is one horizontal scanning period) is equal to or shorter than 1.2 ms.

11. The liquid crystal display device of claim 7, wherein if the number of horizontal scanning periods included in one vertical scanning period is Nv-total, then (Nsv/Nv-total)×

one vertical scanning period is equal to or shorter than 1.2 ms.

12. The liquid crystal display device of claim 7, wherein if the number of horizontal scanning periods included in one effective display period is Nv-Disp, then Nv-Disp is an integral number of times as large as Nsv×

2.

13. The liquid crystal display device of claim 1, wherein in an arbitrary vertical scanning period, source signal voltages supplied to two source bus lines that are associated with mutually adjacent columns of pixels have opposite polarities.

14. The liquid crystal display device of claim 1, wherein one vertical scanning sub-period is equal or shorter than 1/120 second.

15. A TV receiver comprising:

the liquid crystal display device of claim 1; and

a tuner, which receives a TV broadcast and outputs a video signal to the liquid crystal display device.

16. A liquid crystal display device comprising:

a number of pixels that are arranged in columns and rows to form a matrix pattern;

a plurality of source bus lines, each of which is associated with one of the columns of pixels; and

a plurality of gate bus lines, each of which is associated with one of the rows of pixels,

wherein the pixels are scanned by supplying gate signal voltages to the respective gate bus lines, and

wherein each vertical scanning period has multiple vertical scanning sub-periods including a first vertical scanning sub-period for sequentially scanning a series of odd or even rows of pixels and a second vertical scanning sub-period, which is continuous with the first vertical scanning sub-period, for sequentially scanning even or odd rows of pixels that have been skipped during the first vertical scanning sub-period, and

wherein the polarity of a source signal voltage supplied to each said source bus line changes in a predetermined sequence, which includes a series of two vertical scanning sub-periods in which the source signal voltage has mutually opposite polarities, and

wherein each said pixel includes first and second subpixels, and a plurality of TFTs, each of which is associated with one of the first and second subpixels of that pixel, and

wherein two pixels that are adjacent to each other along their associated one of the source bus lines are arranged such that either the respective first subpixels or the respective second subpixels are adjacent to each other along the source bus line.

17. The liquid crystal display device of claim 16, wherein the first and second subpixels are arranged along the source bus line, and a pixel that is adjacent to the first subpixel along the source bus line is not adjacent to the second subpixel.

18. The liquid crystal display device of claim 16, wherein the first and second subpixels are arranged so as to interpose between them one of the gate bus lines that is associated with the pixel including the first and second subpixels.

19. The liquid crystal display device of claim 16, wherein along the source bus line, the second subpixel is interposed between two portions of the first subpixel, and

wherein each pair of pixels is arranged along the source bus line so that the first subpixels thereof are adjacent to each other along the source bus line.

20. The liquid crystal display device of claim 16, further comprising a plurality of auxiliary lines, each of which is arranged between two associated pixels that are adjacent to each other along the source bus line and is controlled to have a predetermined potential level.

21. The liquid crystal display device of claim 20, wherein the auxiliary lines are a plurality of CS bus lines, each of which is associated with either the respective first subpixels or the respective second subpixels of one of the rows of pixels.

22. The liquid crystal display device of claim 21, wherein the CS bus lines include at least one CS bus line that is associated in common with two subpixels that belong to two different pixels and that are adjacent to each other in the column direction.

23. The liquid crystal display device of claim 22, wherein supposing a certain row formed by some of the pixels is an n^th row, a storage capacitor line, to which the storage capacitor counter electrode of the first subpixel of the pixel that is located at the intersection between an arbitrary column and the n^th row is connected, is identified by CSBL_(n)A and a storage capacitor line, to which the storage capacitor counter electrode of the second subpixel thereof is connected, is identified by CSBL_(n)B,

CS bus lines that are connected to L electrically independent storage capacitor trunks satisfy

24. A gate driver comprising:

a first shift register for odd stages and a second shift register for even stages, the first and second shift registers receiving clock signals and start pulses independently of each other and a control signal in common;

a first AND gate that receives the output of one of the first and second shift registers and a logically inverted one of the control signal; and

a second AND gate that receives the output of the other shift register and a logically inverted one of the control signal that has already had its logic inverted,

wherein the respective outputs of the first and second AND gates correspond to signals to be output to their associated gate bus lines.

25. The gate driver of claim 24, wherein it is determined by the control signal whether output needs to be provided from an odd stage through the first shift register or an even stage through the second shift register.