LIQUID CRYSTAL DISPLAY
First Claim
1. A liquid crystal display device comprising:
- a number of pixels that are arranged in columns and rows to form a matrix pattern, each said pixel including first and second subpixels that are able to exhibit mutually different luminances at least at a certain grayscale;
a plurality of source bus lines, each of which is associated with one of the columns of pixels;
a plurality of gate bus lines, each of which is associated with one of the rows of pixels;
a plurality of TFTs, each of which is associated with one of the first and second subpixels of an associated one of the pixels; and
a plurality of CS bus lines, each of which is associated with either the respective first subpixels or the respective second subpixels of one of the rows of pixels, andwherein each of the first and second subpixels includes a liquid crystal capacitor and a storage capacitor, andwherein the CS bus lines connected to the respective storage capacitors of the first and second subpixels are electrically independent of each other, andwherein the pixels are scanned by supplying gate signal voltages to the respective gate bus lines; and
wherein a CS voltage supplied to each said CS bus line has a waveform, of which the polarity changes at least once a vertical scanning period, andwherein each said vertical scanning period has multiple vertical scanning sub-periods including a first vertical scanning sub-period for sequentially scanning a series of odd or even rows of pixels and a second vertical scanning sub-period, which is continuous with the first vertical scanning sub-period, for sequentially scanning even or odd rows of pixels that have been skipped during the first vertical scanning sub-period, andwherein the polarity of a source signal voltage supplied to each said source bus line changes in a predetermined sequence, which includes a series of two vertical scanning periods or sub-periods in which the source signal voltage has mutually opposite polarities, andwherein the CS voltage has a waveform that alternately performs the function of increasing or decreasing the effective voltage of one of two subpixels, which is associated with a CS bus line supplied with the CS voltage, in each of pixels that are connected to a jth gate bus line to be selected during the first vertical scanning sub-period, and the function of increasing or decreasing the effective voltage of one of two subpixels, which is associated with a CS bus line supplied with the CS voltage, in each of pixels that are connected to a (j+1)th gate bus line to be selected during the second vertical scanning sub-period.
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Accused Products
Abstract
In one embodiment of the present invention, each pixel includes first and second subpixels. CS bus lines connected to the respective storage capacitors of the first and second subpixels are electrically independent of each other. A CS voltage has a waveform that inverts its polarity at least once a frame, which includes a first subframe for sequentially scanning a series of odd rows and a second SF for sequentially scanning even rows that have been skipped during the first SF. A source signal voltage varies so as to have two frames or subframes with mutually opposite polarities. A CS voltage has a waveform that has quite opposite consequences on the effective voltage of a subpixel of a pixel connected to the jth scan line to be selected during the first subframe and on that of another subpixel of a pixel connected to the (j+1)th scan line to be selected during the second subframe. In this manner, the deterioration in display quality, which would be caused if either a source line inversion drive or a block inversion drive is applied to a multi-pixel technology, can be minimized.
118 Citations
25 Claims
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1. A liquid crystal display device comprising:
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a number of pixels that are arranged in columns and rows to form a matrix pattern, each said pixel including first and second subpixels that are able to exhibit mutually different luminances at least at a certain grayscale; a plurality of source bus lines, each of which is associated with one of the columns of pixels; a plurality of gate bus lines, each of which is associated with one of the rows of pixels; a plurality of TFTs, each of which is associated with one of the first and second subpixels of an associated one of the pixels; and a plurality of CS bus lines, each of which is associated with either the respective first subpixels or the respective second subpixels of one of the rows of pixels, and wherein each of the first and second subpixels includes a liquid crystal capacitor and a storage capacitor, and wherein the CS bus lines connected to the respective storage capacitors of the first and second subpixels are electrically independent of each other, and wherein the pixels are scanned by supplying gate signal voltages to the respective gate bus lines; and wherein a CS voltage supplied to each said CS bus line has a waveform, of which the polarity changes at least once a vertical scanning period, and wherein each said vertical scanning period has multiple vertical scanning sub-periods including a first vertical scanning sub-period for sequentially scanning a series of odd or even rows of pixels and a second vertical scanning sub-period, which is continuous with the first vertical scanning sub-period, for sequentially scanning even or odd rows of pixels that have been skipped during the first vertical scanning sub-period, and wherein the polarity of a source signal voltage supplied to each said source bus line changes in a predetermined sequence, which includes a series of two vertical scanning periods or sub-periods in which the source signal voltage has mutually opposite polarities, and wherein the CS voltage has a waveform that alternately performs the function of increasing or decreasing the effective voltage of one of two subpixels, which is associated with a CS bus line supplied with the CS voltage, in each of pixels that are connected to a jth gate bus line to be selected during the first vertical scanning sub-period, and the function of increasing or decreasing the effective voltage of one of two subpixels, which is associated with a CS bus line supplied with the CS voltage, in each of pixels that are connected to a (j+1)th gate bus line to be selected during the second vertical scanning sub-period. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A liquid crystal display device comprising:
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a number of pixels that are arranged in columns and rows to form a matrix pattern;
a plurality of source bus lines, each of which is associated with one of the columns of pixels; and
a plurality of gate bus lines, each of which is associated with one of the rows of pixels,wherein the pixels are scanned by supplying gate signal voltages to the respective gate bus lines, and wherein each vertical scanning period has multiple vertical scanning sub-periods including a first vertical scanning sub-period for sequentially scanning a series of odd or even rows of pixels and a second vertical scanning sub-period, which is continuous with the first vertical scanning sub-period, for sequentially scanning even or odd rows of pixels that have been skipped during the first vertical scanning sub-period, and wherein the polarity of a source signal voltage supplied to each said source bus line changes in a predetermined sequence, which includes a series of two vertical scanning sub-periods in which the source signal voltage has mutually opposite polarities, and wherein each said pixel includes first and second subpixels, and a plurality of TFTs, each of which is associated with one of the first and second subpixels of that pixel, and wherein two pixels that are adjacent to each other along their associated one of the source bus lines are arranged such that either the respective first subpixels or the respective second subpixels are adjacent to each other along the source bus line. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23)
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24. A gate driver comprising:
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a first shift register for odd stages and a second shift register for even stages, the first and second shift registers receiving clock signals and start pulses independently of each other and a control signal in common; a first AND gate that receives the output of one of the first and second shift registers and a logically inverted one of the control signal; and a second AND gate that receives the output of the other shift register and a logically inverted one of the control signal that has already had its logic inverted, wherein the respective outputs of the first and second AND gates correspond to signals to be output to their associated gate bus lines. - View Dependent Claims (25)
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Specification