4 F2 MEMORY CELL ARRAY

• US 20100097835A1
• Filed: 10/16/2008
• Published: 04/22/2010
• Est. Priority Date: 10/16/2008
• Status: Active Grant

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Qimonda AG (Infineon Technologies AG)
• Inventors: Schloesser, Till, Popp, Martin
• Granted Patent: US 8,294,188 B2
• Time in Patent Office: Days
• US Class Current: 365/63
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate
• CPC Class Codes: H10B 12/48 Data lines or contacts therefor
• CPC Class Codes: H10B 12/482 Bit lines
• CPC Class Codes: H10B 12/485 Bit line contacts
• CPC Class Codes: H10B 12/488 Word lines

Abstract

An integrated circuit including a memory cell array comprises active area lines, bitlines, the bitlines being arranged so that an individual one intersects a plurality of the active area lines to form bitline-contacts, respectively, the bitlines being arranged at a bitline pitch, wordlines being arranged so that an individual one of the wordlines intersects a plurality of the active area lines, and an individual one of the wordlines intersects a plurality of the bitlines, the wordlines being arranged at a wordline pitch, wherein neighboring bitline-contacts, each of which is connected to one of the active area lines, are connected with different bitlines, and the bitline pitch is different from the wordline pitch.

Claims

1. An integrated circuit including a memory cell array comprising:

active area lines;

bitlines, the bitlines being arranged so that an individual one intersects a plurality of the active area lines to form bitline-contacts, respectively, the bitlines being arranged at a bitline pitch;

wordlines being arranged so that an individual one of the wordlines intersects a plurality of the active area lines, and an individual one of the wordlines intersects a plurality of the bitlines, the wordlines being arranged at a wordline pitch,

wherein neighboring bitline-contacts, each of which is connected to one of the active area lines, are connected with different bitlines, and

the bitline pitch is different from the wordline pitch.

2. The integrated circuit according to claim 1, wherein the wordline pitch is smaller than the bitline pitch.

3. The integrated circuit according to claim 2, wherein the wordline pitch corresponds to ⅔

of the bitline pitch.

4. The integrated circuit according to claim 3, wherein the bitline pitch corresponds to 2 F, and the size of a memory cell corresponds to 4 F*F.

5. The integrated circuit according to claim 1, wherein the active area lines are continuous active area lines.

6. The integrated circuit according to claim 1, wherein the active area lines are straight lines.

7. The integrated circuit according to claim 1, wherein the memory cell array further comprises storage capacitors.

8. The integrated circuit according to claim 7, wherein the storage capacitors are formed over a surface of a semiconductor substrate.

9. The integrated circuit according to claim 1, wherein one bitline-contact is associated with two neighboring transistors that are assigned to one active area line.

10. The integrated circuit of claim 1, wherein the bitlines generally extend along a first direction.

11. The integrated circuit of claim 10, wherein the wordlines extend along a second direction, the second direction being perpendicular to the first direction.

12. The integrated circuit of claim 1, wherein the bitline-contacts that are associated with neighboring bitlines are arranged along one line, this line generally extending along the second direction.

13. The integrated circuit of claim 1, further comprising capacitor contacts that are configured to connect the transistors with corresponding capacitors, wherein the capacitor contacts are disposed along lines extending in the second direction.

14. The integrated circuit according to claim 1, wherein the wordlines are formed as buried wordlines.

15. The integrated circuit of claim 1, further comprising isolation gatelines which are adapted to isolate neighboring transistors from each others, the isolation gatelines being arranged in parallel with the wordlines.

16. An integrated circuit including a memory cell array comprising:

bitlines generally extending along a first direction, the bitlines being arranged at a bitline pitch;

wordlines running along a second direction, the wordlines being arranged at a wordline pitch;

active areas, transistors being formed in the active areas, the active areas extending in a direction that is slanted with respect to the first and second directions,

bitline contacts, the bitline contacts being disposed in region generally defined by an intersection of a bitline and a corresponding active area;

wherein neighboring bitline contacts that are shifted along a direction that is slanted with respect to the first and second directions, respectively, are connected with neighboring bitlines; and

the bitline pitch is different from the wordline pitch.

17. The integrated circuit according to claim 16, wherein the wordline pitch is smaller than the bitline pitch.

18. The integrated circuit according to claim 17, wherein the wordline pitch corresponds to ⅔

of the bitline pitch.

19. The integrated circuit according to claim 18, wherein the bitline pitch corresponds to 2 F, and the size of a memory cell corresponds to 4 F*F.

20. The integrated circuit according to claim 16, wherein the active area lines are continuous active area lines.

21. The integrated circuit according to claim 16, wherein the active area lines are straight lines.

22. The integrated circuit according to claim 16, wherein the memory cell array further comprises storage capacitors.

23. The integrated circuit according to claim 22, wherein the storage capacitors are formed over a surface of a semiconductor substrate.

24. The integrated circuit according to claim 16, wherein one bitline contact is associated with two neighboring transistors that are assigned to one active area line.

25. The integrated circuit of claim 16, wherein the bitline-contacts that are associated with neighboring bitlines are arranged along one line, this line generally extending along the second direction.

26. The integrated circuit of claim 16, further comprising capacitor contacts that are configured to connect the transistors with corresponding capacitors, wherein the capacitor contacts are disposed along lines extending in the second direction.

27. The integrated circuit according to claim 16, wherein the wordlines are formed as buried wordlines.

28. The integrated circuit of claim 16, further comprising isolation gatelines which are adapted to isolate neighboring transistors from each others, the isolation gatelines being arranged in parallel with the wordlines.

29. An integrated circuit including a memory cell array comprising:

bitlines generally extending along a first direction, the bitlines being arranged at a bitline pitch;

wordlines running along a second direction, the wordlines being arranged at a wordline pitch, the wordlines being disposed so that a bottom side of the wordlines is disposed below a substrate surface;

the bitlines and the wordlines being connected with corresponding memory cells;

wherein the bitline pitch is different from the wordline pitch.

30. The integrated circuit according to claim 29, wherein the wordline pitch is smaller than the bitline pitch.

31. The integrated circuit according to claim 30, wherein the wordline pitch corresponds to ⅔

of the bitline pitch.

33. The integrated circuit according to claim 29, wherein the active area lines are continuous active area lines.

34. The integrated circuit according to claim 29, wherein the active area lines are straight lines.

35. The integrated circuit according to claim 29, wherein the memory cell array further comprises storage capacitors.

36. The integrated circuit according to claim 35, wherein the storage capacitors are formed over a surface of a semiconductor substrate.

37. The integrated circuit according to claim 29, wherein one bitline contact is associated with two neighboring transistors that are assigned to one active area line.

38. The integrated circuit of claim 29, wherein the bitline-contacts that are associated with neighboring bitlines are arranged along one line, this line generally extending along the second direction.

39. The integrated circuit of claim 29, further comprising capacitor contacts that are configured to connect the transistors with corresponding capacitors, wherein the capacitor contacts are disposed along lines extending in the second direction.

40. The integrated circuit of claim 29, further comprising isolation gatelines which are adapted to isolate neighboring transistors from each others, the isolation gatelines being arranged in parallel with the wordlines.

41. The integrated circuit according to claim 29, wherein an upper side of the wordlines is disposed below the substrate surface.

32. The integrated circuit according to claim 32, wherein the bitline pitch corresponds to 2 F, and the size of a memory cell corresponds to 4 F*F.