Memory Bitcell and Method of Using the Same

• US 20100097836A1
• Filed: 08/03/2006
• Published: 04/22/2010
• Est. Priority Date: 08/03/2005
• Status: Abandoned Application

• Current Assignee: Charles Smith
• Original Assignee: Charles Smith
• Inventors: Smith, Charles
• Application Number:
  US11/989,878
• Publication Number:
  US 20100097836A1
• Time in Patent Office: Days
• US Class Current: 365/104
• CPC Class Codes: G11C 17/14 in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
• CPC Class Codes: G11C 17/146 Write once memory, i.e. allowing changing of memory content by writing additional bits
• CPC Class Codes: G11C 23/00 Digital stores characterised by movement of mechanical parts to effect storage, e.g. using balls; Storage elements therefor

Abstract

A memory bitcell comprises first (102) and second (103) transistors and a cantilever module (104) having two states. The first transistor (102) is arranged to communicate a first signal to the input of the cantilever module (104) upon receipt of a second signal. The second transistor (103) is arranged to bypass the cantilever module (104) upon receipt of a third signal (RST). The memory bitcell is operable such that the state of the cantilever (104) can be changed in order to represent one bit of binary information and can be detected by monitoring the first signal.

Claims

1. A memory bitcell comprising:

first and second transistors; and

a cantilever module having two states, wherein the first transistor is arranged to communicate a first signal to an input of the cantilever module upon receipt of a second signal and the second transistor is arranged to bypass the cantilever module upon receipt of a third signal, such that the state of the cantilever module can be changed in order to represent one bit of binary information and can be detected by monitoring the first signal.

2. The memory bitcell according to claim 1, wherein:

a gate of the first transistor is connected to a wordline;

a source of the first transistor is connected to a bitline;

a drain of the first transistor is connected to both a first terminal of the cantilever module and a source of the second transistor; and

a drain of the second transistor is connected to a second terminal of the cantilever module.

7. The memory bitcell of claim 1, further comprising:

a charging transistor configured to communicate the first signal to the first transistor.

3. (canceled)

4. (canceled)

5. A memory bitcell comprising:

a first MOS transistor having a drain terminal, a gate terminal, and a source terminal, the gate terminal of the first MOS transistor is configured to receive a first control signal, and wherein the first control signal is used to turn ON the first MOS transistor;

a second MOS transistor having a drain terminal, a gate terminal, and a source terminal, wherein the drain terminal of the second MOS transistor is connected to the source terminal of the first MOS transistor, and the gate terminal of the second MOS transistor is configured to receive a second control signal, wherein the second control signal is used to turn ON the second MOS transistor; and

a cantilever module having two states, and wherein the cantilever module includes a first terminal and a second terminal, and wherein the first terminal is connected to the source terminal of the first MOS transistor, and the second terminal is connected to the source terminal of the second MOS transistor.

6. The memory bitcell of claim 5 wherein the first and second MOS transistors are N-channel MOS transistors.

8. The memory bitcell of claim 5, further comprising:

a charging MOS transistor having a drain terminal, a gate terminal, and a source terminal, wherein the source terminal of the charging MOS transistor is connected to the drain terminal of the first MOS transistor, the drain terminal of the charging MOS transistor is configured to receive a first signal, and the gate terminal of the charging MOS transistor is configured to receive a third control signal, wherein the third control signal is used to turn on the charging MOS transistor to communicate the first signal to the drain terminal of the first MOS transistor.

9. A memory array having a plurality of memory bitcells, each memory bitcell comprising:

first and second transistors;

a cantilever module having two states, wherein the first transistor is arranged to communicate a first signal to an input of the cantilever module upon receipt of a second signal and the second transistor is arranged to bypass the cantilever module upon receipt of a third signal, such that a state of the cantilever can be changed in order to represent one bit of binary information and can be detected by monitoring the first signal;

wherein the gate of the first transistor is connected to a wordline, the source of the first transistor is connected to a bitline, the drain of the first transistor is connected to both a first terminal of the cantilever module and the source of the second transistor, and the drain of the second transistor is connected to a second terminal of the cantilever module.

10. The memory array of claim 9, wherein the first and second transistors are N-channel MOS transistors.

11. The memory array of claim 9, wherein each memory bitcell further comprises a charging transistor arranged to communicate the first signal to the first transistor.