High speed ferroelectric random access memory
First Claim
1. A memory device, comprising:
- a memory cell including a pass transistor and a ferroelectric capacitor based on a ferroelectric material, wherein the ferroelectric capacitor is composed of a first plate connecting to the pass transistor and a second plate connecting to a plate line; and
a non-inverting local sense amp including a first inverting amplifier and a second inverting amplifier, wherein the first inverting amplifier includes an inverter having a first amplify transistor and a pull-up transistor for reading the memory cell through a local bit line when reading, a local pre-charge transistor for pre-charging the local bit line, and a write transistor for driving the local bit line when writing; and
the second inverting amplifier includes a second amplify transistor for reading an amplify node connecting to an output node of the inverter, and a local enable transistor is serially connected to the second amplify transistor for enabling, where the local enable transistor is connected to a global bit line; and
a global sense amp for reading an output from the non-inverting local sense amp through the global bit line, wherein the global sense amp includes a global reset transistor for resetting the global bit line, a cross coupled inverter latch for storing an output from a bit read circuit connecting to the global bit line and for sending a write data to a bit write circuit driving the global bit line, a data transfer circuit for transferring a read output from the cross coupled inverter latch to a forwarding read line through a read selector and a read buffer, and a data receive circuit for sending a write input to the cross coupled inverter latch from a forwarding write line through a receive switch; and
a locking signal generator for locking the bit read circuit with a locking signal which is generated by a delay circuit receiving the read output from the cross coupled inverter latch.
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Abstract
For realizing high speed ferroelectric random access memory, bit line is multi-divided for reducing parasitic capacitance, so that the bit line is quickly charged or discharged by a memory cell including a ferroelectric capacitor when reading. Particularly, a non-inverting local sense amp is devised for reducing area, such that the memory cell is read by the local sense amp through a lightly loaded local bit line, and the local sense amp is read by a global sense amp through a global bit line. By the sense amps, a voltage difference in the local bit line is converted to a time difference for differentiating data “1” and data “0”, and buffered data path is used for achieving fast data transfer. Additionally, various alternative circuits and memory cell structures for implanting the memory are described.
35 Citations
20 Claims
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1. A memory device, comprising:
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a memory cell including a pass transistor and a ferroelectric capacitor based on a ferroelectric material, wherein the ferroelectric capacitor is composed of a first plate connecting to the pass transistor and a second plate connecting to a plate line; and a non-inverting local sense amp including a first inverting amplifier and a second inverting amplifier, wherein the first inverting amplifier includes an inverter having a first amplify transistor and a pull-up transistor for reading the memory cell through a local bit line when reading, a local pre-charge transistor for pre-charging the local bit line, and a write transistor for driving the local bit line when writing; and
the second inverting amplifier includes a second amplify transistor for reading an amplify node connecting to an output node of the inverter, and a local enable transistor is serially connected to the second amplify transistor for enabling, where the local enable transistor is connected to a global bit line; anda global sense amp for reading an output from the non-inverting local sense amp through the global bit line, wherein the global sense amp includes a global reset transistor for resetting the global bit line, a cross coupled inverter latch for storing an output from a bit read circuit connecting to the global bit line and for sending a write data to a bit write circuit driving the global bit line, a data transfer circuit for transferring a read output from the cross coupled inverter latch to a forwarding read line through a read selector and a read buffer, and a data receive circuit for sending a write input to the cross coupled inverter latch from a forwarding write line through a receive switch; and a locking signal generator for locking the bit read circuit with a locking signal which is generated by a delay circuit receiving the read output from the cross coupled inverter latch. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification