Method to manufacture split gate with high density plasma oxide layer as inter-polysilicon insulation layer

• US 20100099230A1
• Filed: 10/16/2009
• Published: 04/22/2010
• Est. Priority Date: 12/22/2006
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Wang, Yu, Tai, Sung-Shan, Hébert, François, Chang, Hong, Pan, Mengyu, Hu, Yong-Zhong, Lou, Yingying
• Granted Patent: US 8,053,315 B2
• Time in Patent Office: Days
• US Class Current: 438/270
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

This invention discloses a method of manufacturing a trenched semiconductor power device with split gate filling a trench opened in a semiconductor substrate wherein the split gate is separated by an inter-poly insulation layer disposed between a top and a bottom gate segments. The method further includes a step of forming the inter-poly layer by applying a RTP process after a HDP oxide deposition process to bring an etch rate of the HDP oxide layer close to an etch rate of a thermal oxide.

Claims

1. A method for manufacturing a trenched semiconductor power device comprising step of opening a trench in a semiconductor substrate and said method further comprising:

filling said trench with a trenching filling material followed by an etch back process to remove from a top portion of said trench until a desired depth is reached; and

depositing a high density plasma (HDP) oxide layer followed by an annealing densification process at an elevated temperature for increasing an etch rate of said HDP oxide layer to be substantially the same as an etch rate of a thermal oxide.

2. The method of claim 1 wherein:

said step of annealing densification process further comprising a step of carrying out said annealing densification process in a N2 of O2/N2 ambient environment to carry out a wet oxidation.

3. The method of claim 1 wherein:

said step of annealing densification process further comprising a step of carrying out said annealing densification process in a N2 of O2/N2 ambient environment at a temperature above 850 degrees Celsius for approximately 30 seconds to carry out a RTP process.

4. The method of claim 1 wherein:

said step of annealing densification process further comprising a precisely controlled RTP anneal process whereby said HDP oxide layer having substantially a same etch rate as an etch rate of a thermal oxide.

5. The method of claim 1 further comprising:

dry etching back said HDP oxide layer to expose said HDP oxide layer followed by a dry or wet-etch to obtain a desired HDP oxide layer thickness.

6. The method of claim 4 further comprising:

applying a chemical-mechanical planarization (CMP) process on said HDP oxide layer.

7. The method of claim 1 wherein:

said step of filling said trench with a trench filling material further comprising a step of filling said trench with an un-doped polysilicon then doping said polysilicon with POCL3 followed by implanting phosphorous or boron ions.

8. The method of claim 1 wherein:

said step of etching back to remove said trench filling material from a top portion of said trench further forming an over-etching pocket along sidewalls of said trench near a top portion of a bottom portion of said trench-filling material; and

said step of depositing a high density plasma (HDP) oxide layer further comprising a step of filling said over-etching pocket for improving a device ruggedness of said semiconductor power device.

9. The method of claim 1 further comprising:

filling said trench on top of said inter-segment insulation layer to form at least two mutually insulated trench-filling segments constituting a split gate for said semiconductor device.

10. The method of claim 9 further comprising:

implanting a source region surrounding said split gate and impaling a body region encompassing said source region for manufacturing said semiconductor power device as a trenched metal oxide semiconductor field effect transistor (MOSFET) device.

11. The method of claim 1 further comprising:

growing a thermal oxide layer along a bottom and sidewall of said trench;

depositing a HDP oxide layer overlaying said thermal oxide layer;

removing oxide layers along trench sidewall;

re-growing a thermal oxide layer along said trench sidewall whereas said thermal oxide layer along side trench sidewall is thinner than said HDP oxide layer at said trench bottom.

12. A method for manufacturing a trenched semiconductor power device with split gate filling a trench opened in a semiconductor substrate wherein the split gate is separated by an inter-poly insulation layer separating a top and a bottom gate segments, the method further comprising:

forming said inter-poly layer by applying a RTP process after a HDP oxide deposition process to bring an etch rate of the HDP oxide layer close to an etch rate of a thermal oxide.