Victim Cache Replacement

• US 20100100682A1
• Filed: 10/22/2008
• Published: 04/22/2010
• Est. Priority Date: 10/22/2008
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: McNeil, William L., Starke, William J., Stuecheli, Jeffrey A., Guthrie, Guy L., Patel, Piyush C., Jeremiah, Thomas L.
• Granted Patent: US 8,347,037 B2
• Time in Patent Office: Days
• US Class Current: 711/122
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811
• CPC Class Codes: G06F 12/128 adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
• CPC Class Codes: G06F 2212/1028 Power efficiency
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A data processing system includes a processor core having an associated upper level cache and a lower level victim cache. In response to a memory access request of the processor core that specifies a non-modifying access to a target coherency granule, a determination is made whether the memory access request hits or misses in a directory of the lower level victim cache. In response to determining that the memory access request hits in the lower level victim cache in a data-valid coherence state, the lower level victim cache provides the target coherency granule of the memory access request to the upper level cache. The lower level victim cache preserves the target coherency granule in the lower level victim cache in a shared coherence state if the memory access request is of a first type and invalidates the target coherency granule if the memory access request is of a second type.

Claims

1. A method of data processing in a data processing system including a processor core having an associated upper level cache and a lower level victim cache, said method comprising:

in response to a memory access request of the processor core that specifies a non-modifying access to a target coherency granule, determining whether the memory access request hits or misses in a directory of the lower level victim cache;

in response to determining that the memory access request hits in the lower level victim cache in a data-valid coherence state;

the lower level victim cache providing the target coherency granule of the memory access request to the upper level cache; and

the lower level victim cache preserving the target coherency granule in the lower level victim cache in a shared coherence state if the memory access request is of a first type and the lower level victim cache invalidating the target coherency granule if the memory access request is of a second type.

2. The method of claim 1, wherein:

the first type comprises a demand load request of the processor core generated in response to processing an instruction in the processor core; and

the second type comprises a prefetch request of the processor core.

3. The method of claim 2, wherein the second type comprises a prefetch request of a store prefetch stream.

4. The method of claim 1, wherein the first type comprises an instruction fetch request.

5. The method of claim 1, wherein the first type comprises a translation fetch request.

6. The method of claim 1, and further comprising;

in response to determining that the memory access request hits in the lower level victim cache in a data-valid coherence state and if the memory access request is of a first type, updating a replacement order of the target coherency granule in the lower level victim cache to a position other than most recently used.

7. The method of claim 1, wherein:

the data processing system includes a system memory;

said step of invalidating the target coherency granule if the memory access request is of a second type comprises invalidating the target coherency granule if the memory access request is of a second type and the target coherency granule is modified with respect to a corresponding memory block in the system memory.

8. A processing unit for a data processing system, the processing unit comprising:

a processor core; and

a cache hierarchy coupled to the processor core to provide low latency data access, the cache hierarchy including an upper level cache coupled to the processor core and a lower level victim cache coupled to the upper level cache, each of the upper level cache and the lower level victim cache including a respective cache directory and a respective data array, wherein the lower level victim cache, responsive to a memory access request of the processor core that specifies a non-modifying access to a target coherency granule, determines whether the memory access request hits or misses in a directory of the lower level victim cache, and wherein responsive to determining that the memory access request hits in the lower level victim cache in a data-valid coherence state, the lower level victim cache provides the target coherency granule of the memory access request to the upper level cache and preserves the target coherency granule in the lower level victim cache in a shared coherence state if the memory access request is of a first type and invalidates the target coherency granule if the memory access request is of a second type.

9. The processing unit of claim 8, wherein:

the first type comprises a demand load request of the processor core generated in response to processing an instruction in the processor core; and

the second type comprises a prefetch request of the processor core.

10. The processing unit of claim 9, wherein the second type comprises a prefetch request of a store prefetch stream.

11. The processing unit of claim 8, wherein the first type comprises an instruction fetch request.

12. The processing unit of claim 8, wherein the first type comprises a translation fetch request.

13. The processing unit of claim 8, wherein the lower level victim cache, responsive to determining that the memory access request hits in the lower level victim cache in a data-valid coherence state and that the memory access request is of a first type, updates a replacement order of the target coherency granule in the lower level victim cache to a position other than most recently used.

14. The processing unit of claim 8, wherein:

the data processing system includes a system memory;

the lower level victim cache invalidates the target coherency granule if the memory access request is of a second type and if the target coherency granule is modified with respect to a corresponding memory block in the system memory.

15. A data processing system, comprising:

at least one system memory; and

a plurality of processing units coupled to the system memory, wherein a processing unit among the plurality of processing units includes;

a processor core; and

a cache hierarchy coupled to the processor core to provide low latency data access, the cache hierarchy including an upper level cache coupled to the processor core and a lower level victim cache coupled to the upper level cache, each of the upper level cache and the lower level victim cache including a respective cache directory and a respective data array, wherein the lower level victim cache, responsive to a memory access request of the processor core that specifies a non-modifying access to a target coherency granule, determines whether the memory access request hits or misses in a directory of the lower level victim cache, and wherein responsive to determining that the memory access request hits in the lower level victim cache in a data-valid coherence state, the lower level victim cache provides the target coherency granule of the memory access request to the upper level cache and preserves the target coherency granule in the lower level victim cache in a shared coherence state if the memory access request is of a first type and invalidates the target coherency granule if the memory access request is of a second type.

16. The data processing system of claim 15, wherein:

the first type comprises a demand load request of the processor core generated in response to processing an instruction in the processor core; and

the second type comprises a prefetch request of the processor core.

17. The data processing system of claim 16, wherein the second type comprises a prefetch request of a store prefetch stream.

18. The data processing system of claim 15, wherein the first type comprises an instruction fetch request.

19. The data processing system of claim 15, wherein the first type comprises a translation fetch request.

20. The data processing system of claim 15, wherein:

the data processing system includes a system memory;

the lower level victim cache invalidates the target coherency granule if the memory access request is of a second type and if the target coherency granule is modified with respect to a corresponding memory block in the system memory.