Victim Cache Prefetching

• US 20100100683A1
• Filed: 10/22/2008
• Published: 04/22/2010
• Est. Priority Date: 10/22/2008
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Williams, Philip G., Starke, William J., Stuecheli, Jeffrey A., Guthrie, Guy L.
• Granted Patent: US 8,209,489 B2
• Time in Patent Office: Days
• US Class Current: 711/122
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A processing unit for a multiprocessor data processing system includes a processor core and a cache hierarchy coupled to the processor core to provide low latency data access. The cache hierarchy includes an upper level cache coupled to the processor core and a lower level victim cache coupled to the upper level cache. In response to a prefetch request of the processor core that misses in the upper level cache, the lower level victim cache determines whether the prefetch request misses in the directory of the lower level victim cache and, if so, allocates a state machine in the lower level victim cache that services the prefetch request by issuing the prefetch request to at least one other processing unit of the multiprocessor data processing system.

Claims

1. A processing unit for a multiprocessor data processing system, said processing unit comprising:

a processor core; and

a cache hierarchy coupled to the processor core to provide low latency data access, the cache hierarchy including an upper level cache coupled to the processor core and a lower level victim cache coupled to the upper level cache, each of the upper level cache and the lower level victim cache including a respective cache directory and a respective data array, wherein responsive to a prefetch request of the processor core that misses in the upper level cache, the lower level victim cache determines whether the prefetch request misses in the directory of the lower level victim cache and, if so, allocates a state machine in the lower level victim cache that services the prefetch request by issuing the prefetch request to at least one other processing unit of the multiprocessor data processing system.

2. The processing unit of claim 1, wherein:

the upper level cache is a level two (L2) cache; and

the lower level victim cache is a level three (L3) victim cache.

3. The processing unit of claim 1, wherein the state machine in the lower level cache is a prefetch machine dedicated to managing servicing of prefetch requests.

4. The processing unit of claim 1, wherein the processing unit, responsive to receiving a target memory block requested by the prefetch request, installs the target memory block in the data array of the lower level victim cache but not in the data array of the upper level cache.

5. The processing unit of claim 3, wherein:

the prefetch request is a leading prefetch request;

the processor core includes a streaming prefetcher that generates the leading prefetch request and a trailing prefetch request both targeting the target memory block.

6. The processing unit of claim 5, wherein the lower level victim cache, responsive to receipt of the trailing prefetch request, provides the target memory block to the upper level cache and preserves the target memory block in the lower level victim cache in a shared coherence state.

8. A data processing system, comprising:

at least one system memory; and

a plurality of processing units coupled to the system memory, wherein a processing unit among the plurality of processing units includes;

a processor core; and

a cache hierarchy coupled to the processor core to provide low latency data access, the cache hierarchy including an upper level cache coupled to the processor core and a lower level victim cache coupled to the upper level cache, each of the upper level cache and the lower level victim cache including a respective cache directory and a respective data array, wherein responsive to a prefetch request of the processor core that misses in the upper level cache, the lower level victim cache determines whether the prefetch request misses in the directory of the lower level victim cache and, if so, allocates a state machine in the lower level victim cache that services the prefetch request by issuing the prefetch request to at least one other processing unit of the data processing system.

7. The processing unit of claim 9, wherein the lower level cache memory, responsive to the trailing prefetch request, updates a replacement order of the target memory block to a position other than most recently used.

9. The data processing system of claim 8, wherein:

the upper level cache is a level two (L2) cache; and

the lower level victim cache is a level three (L3) victim cache.

10. The data processing system of claim 8, wherein the state machine in the lower level cache is a prefetch machine dedicated to managing servicing of prefetch requests.

11. The data processing system of claim 8, wherein the processing unit, responsive to receiving a target memory block requested by the prefetch request, installs the target memory block in the data array of the lower level victim cache but not in the data array of the upper level cache.

12. The data processing system of claim 11, wherein:

the prefetch request is a leading prefetch request;

the processor core includes a streaming prefetcher that generates the leading prefetch request and a trailing prefetch request both targeting the target memory block.

13. The data processing system of claim 12, wherein the lower level victim cache, responsive to receipt of the trailing prefetch request, provides the target memory block to the upper level cache and preserves the target memory block in the lower level victim cache in a shared coherence state.

14. The data processing system of claim 13, wherein the lower level cache memory, responsive to the trailing prefetch request, updates a replacement order of the target memory block to a position other than most recently used.

15. A method of data processing in a multiprocessor data processing system containing a processing unit including a processor core and a cache hierarchy coupled to the processor core to provide low latency data access, wherein the cache hierarchy includes an upper level cache coupled to the processor core and a lower level victim cache coupled to the upper level cache, each of the upper level cache and the lower level victim cache including a respective cache directory and a respective data array, said method comprising:

the lower level victim cache receiving a prefetch request of the processor core that misses in the upper level cache;

in response to receiving the prefetch request, the lower level victim cache determines whether the prefetch request misses in the directory of the lower level victim cache; and

if a determination is made that the prefetch request misses in the directory of the lower level victim cache, allocating a state machine in the lower level victim cache that services the prefetch request by issuing the prefetch request to at least one other processing unit of the multiprocessor data processing system.

16. The method of claim 15, wherein:

the upper level cache is a level two (L2) cache;

the lower level victim cache is a level three (L3) victim cache; and

said receiving step comprises receiving the prefetch request at the L3 victim cache.

17. The method of claim 15, wherein:

the state machine in the lower level cache is a prefetch machine dedicated to managing servicing of prefetch requests; and

the method further comprises allocating the prefetch machine from a pool containing a plurality of prefetch machines.

18. The method of claim 15, said method further comprising:

in response to receiving a target memory block requested by the prefetch request, installing the target memory block in the data array of the lower level victim cache but not in the data array of the upper level cache.

19. The method of claim 18, wherein:

the prefetch request is a leading prefetch request;

the method further comprising a streaming prefetcher in the processor core generating the leading prefetch request and a subsequent trailing prefetch request both targeting the target memory block.

20. The method of claim 19, and further comprising:

the lower level victim cache, responsive to receipt of the trailing prefetch request, providing the target memory block to the upper level cache and preserving the target memory block in the lower level victim cache in a shared coherence state.