GENERIC NON-VOLATILE SERVICE LAYER

• US 20100100857A1
• Filed: 10/16/2008
• Published: 04/22/2010
• Est. Priority Date: 10/16/2008
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Li, Hai, Liu, Hongyue, Xi, Haiwen, Chen, Yiran, Setiadi, Dadi
• Granted Patent: US 7,966,581 B2
• Time in Patent Office: Days
• US Class Current: 716/136
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/333 Design for testability [DFT], e.g. scan chain or built-in self-test [BIST]

Abstract

Method and apparatus for constructing and operating an integrated circuit in an electronic device. In some embodiments, a generic service layer is integrated in a three dimensional integrated circuit and tested using a testing pattern stored in a non-volatile memory. The generic service layer is reconfigured to a permanent non-testing functional component of the integrated circuit.

Claims

1. A method comprising:

integrating a generic service layer in a three dimensional integrated circuit;

testing the integrated circuit using a testing pattern stored in a non-volatile memory; and

reconfiguring the generic service layer to a permanent non-testing functional component of the integrated circuit.

2. The method of claim 1, wherein the non-volatile memory is a spin torque random access memory (STRAM).

3. The method of claim 1, wherein the non-volatile memory is a resistive random access memory (RRAM).

4. The method of claim 1, wherein the integrated circuit is a chip package.

5. The method of claim 1, wherein the non-testing functional component comprises a field programmable gate array (FPGA).

6. The method of claim 5, wherein an array of look-up tables are each connected to a delay flip flop.

7. The method of claim 1, wherein the non-testing functional component is a redundancy correction.

8. The method of claim 1, wherein testing the integrated circuit comprises using an array of unit test structures.

9. The method of claim 1, wherein the integrated circuit is installed on a printed circuit board.

10. The method of claim 1, wherein the non-testing functional component is a security protocol.

11. An apparatus comprising a three dimensional integrated circuit comprising a generic non-volatile service layer affixed to a host layer in a multi-layer integrated circuit chip package, wherein the generic non-volatile service layer is configured in a first configuration to test the host layer using a test pattern stored in a non-volatile memory, and then to be reconfigured in a second configuration as a permanent non-testing functional component of the integrated circuit.

12. The apparatus of claim 11, wherein the non-volatile memory is a spin torque random access memory (STRAM) of said generic service layer.

13. The apparatus of claim 11, wherein the non-volatile memory is a resistive random access memory (RRAM) of said generic service layer.

14. The apparatus of claim 11, further comprising a control circuit which initially configures the service layer in the first configuration, executes said testing of the host layer, and then places the service layer in the second configuration.

15. The apparatus of claim 11, wherein the non-testing functional component comprises a field programmable gate array (FPGA).

16. The apparatus of claim 15, wherein an array of look-up tables are each connected to a delay flip flop in the generic service layer.

17. The apparatus of claim 11, wherein the non-testing functional component is a redundancy correction for the host layer.

18. The apparatus of claim 11, wherein the generic non-volatile service layer comprises an array of unit test structures when configured in the first configuration to test the host layer.

19. The apparatus of claim 11, wherein the integrated circuit is installed on a printed circuit board.

20. The apparatus of claim 11, wherein the non-testing functional component is a security protocol used by the host layer.