Semiconductor device and passive component integration in a semiconductor package

• US 20100102327A1
• Filed: 06/05/2009
• Published: 04/29/2010
• Est. Priority Date: 02/26/2008
• Status: Active Grant

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Standing, Martin
• Granted Patent: US 9,147,644 B2
• Time in Patent Office: Days
• US Class Current: 257/76
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/0554 External layer
• CPC Class Codes: H01L 2224/0555 Shape
• CPC Class Codes: H01L 2224/0556 Disposition
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/1411 the bump connectors being bonded to at least one common bonding area
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/29026 relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/33181 On opposite sides of the body
• CPC Class Codes: H01L 2224/83851 being an anisotropic conductive adhesive
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 23/492 Bases or plates or solder therefor
• CPC Class Codes: H01L 23/49833 the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/49844 for devices being provided for in H01L29/00
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/31 : Structure, shape, material or disposition of the layer connectors after the connecting process
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/072 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/115 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 25/162 : the devices being mounted on two or more different substrates
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/1033 : Gallium nitride [GaN]
• CPC Class Codes: H01L 2924/1203 : Rectifying Diode
• CPC Class Codes: H01L 2924/1205 : Capacitor
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1533 : the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate

Abstract

According to one exemplary embodiment, a semiconductor package includes a substrate having lower and upper surfaces. The semiconductor package further includes at least one passive component coupled to first and second conductive pads on the upper surface of the substrate. The semiconductor package further includes at least one semiconductor device coupled to a first conductive pad on the lower surface of the substrate. The at least one semiconductor device has a first electrode for electrical and mechanical connection to a conductive pad external to the semiconductor package. The at least one semiconductor device can have a second electrode electrically and mechanically coupled to the first conductive pad on the lower surface of the substrate.

Claims

1. A semiconductor package comprising:

a substrate having lower and upper surfaces;

at least one passive component coupled to first and second conductive pads on said upper surface of said substrate;

at least one semiconductor device coupled to a first conductive pad on said lower surface of said substrate;

said at least one semiconductor device having a first electrode for electrical and mechanical connection to a conductive pad external to said semiconductor package.

2. The semiconductor package of claim 1, wherein said at least one semiconductor device has a second electrode electrically and mechanically coupled to said first conductive pad on said lower surface of said substrate.

3. The semiconductor package of claim 2, wherein said at least one semiconductor device has a third electrode adjacent to said first electrode for electrical and mechanical connection to a conductive pad external to said semiconductor package.

4. The semiconductor package of claim 2, wherein said first and second electrodes of said at least one semiconductor device are situated on opposing surfaces of said at least one semiconductor device.

5. The semiconductor package of claim 1 further comprising an integrated circuit (IC) die situated on said upper surface of said substrate and having a plurality of input/output electrodes.

6. The semiconductor package of claim 5, wherein each of said input/output electrodes is electrically and mechanically coupled to one of a plurality of conductive pads on said upper surface of said substrate.

7. The semiconductor package of claim 5 further comprising a second conductive pad on said lower surface of said substrate, wherein said second conductive pad on said lower surface of said substrate is coupled to one of said plurality of input/output electrodes of said IC die.

8. The semiconductor package of claim 1, wherein said at least one passive component is electrically and mechanically coupled to each of said first and second conductive pads by a conductive adhesive.

9. The semiconductor package of claim 2, wherein said at least one semiconductor device is a FET, wherein said first electrode is a source electrode of said FET and said second electrode is a drain electrode of said FET.

10. The semiconductor package of claim 1, wherein said at least one semiconductor device is a GaN device.

11. A semiconductor package comprising:

a substrate having lower and upper surfaces;

at least one passive component coupled to first and second conductive pads on said upper surface of said substrate;

a first semiconductor device coupled to a first conductive pad on said lower surface of said substrate;

a second semiconductor device coupled to a second conductive pad on said lower surface of said substrate;

said first semiconductor device having a first electrode for electrical and mechanical connection to a conductive pad external to said semiconductor package using a conductive adhesive.

12. The semiconductor package of claim 11, wherein said second semiconductor device has a first electrode for electrical and mechanical connection to a conductive pad external to said semiconductor package.

13. The semiconductor package of claim 11, wherein said first semiconductor device has a second electrode electrically and mechanically coupled to said first conductive pad on said lower surface of said substrate.

14. The semiconductor package of claim 13, wherein said first semiconductor device has a third electrode situated adjacent to said first electrode, wherein said third electrode is for electrical and mechanical connection to a conductive pad external to said semiconductor package.

15. The semiconductor package of claim 12, wherein said second semiconductor device has a second electrode electrically and mechanically coupled to said second conductive pad on said lower surface of said substrate.

16. The semiconductor package of claim 13, wherein said first and second electrodes of said first semiconductor device are situated on opposing surfaces of said first semiconductor device.

17. The semiconductor package of claim 11 further comprising an IC die situated on said upper surface of said substrate and having a plurality of input/output electrodes.

18. The semiconductor package of claim 17, wherein each of said plurality of input/output electrodes is electrically and mechanically coupled to one of a plurality of conductive pads on said upper surface of said substrate.

19. The semiconductor package of claim 11, wherein said at least one passive component is electrically and mechanically coupled to each of said first and second conductive pads by a conductive adhesive.

20. The semiconductor package of claim 11 further comprising a metallic plate situated on said upper surface of said substrate.