APPARATUS FOR USE IN SEMICONDUCTOR WAFER PROCESSING FOR LATERALLY DISPLACING INDIVIDUAL SEMICONDUCTOR DEVICES AWAY FROM ONE ANOTHER

• US 20100102433A1
• Filed: 12/30/2009
• Published: 04/29/2010
• Est. Priority Date: 01/29/2004
• Status: Abandoned Application

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Doan, Trung T.
• Application Number:
  US12/650,179
• Publication Number:
  US 20100102433A1
• Time in Patent Office: Days
• US Class Current: 257/690
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05099 Material
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/056 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/06135 Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 2224/1191 Forming a passivation layer after forming the bump connector
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/29099 Material
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3185 the coating covering also the sidewalls of the semiconductor body
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys

Abstract

A chip-scale or wafer-level package, having passivation layers on substantially all surfaces thereof to form a hermetically sealed package, is provided. The package may be formed by disposing a first passivation layer on the passive or back side surface of a semiconductor wafer. The semiconductor wafer may be attached to a flexible membrane and diced, such as by a wafer saw, to separate the semiconductor devices. Once diced, the flexible membrane may be stretched so as to laterally displace the individual semiconductor devices away from one another and substantially expose the side edges thereof. Once the side edges of the semiconductor devices are exposed, a passivation layer may be formed on the side edges and active surfaces of the devices. A portion of the passivation layer over the active surface of each semiconductor device may be removed so as to expose conductive elements formed therebeneath.

Claims

1. A semiconductor package, comprising:

a semiconductor device including an active surface, a back surface, and a side edge extending from the active surface to the back surface;

at least one bond pad on the active surface of the semiconductor device;

a first passivation material over the active surface of the semiconductor device, the at least one bond pad being exposed through the first passivation material;

a conductive bump secured on the at least one bond pad; and

a second passivation material over the first passivation material, the side edge of the semiconductor device, and at least substantially surrounding the conductive bump.

2. The semiconductor package of claim 1, wherein a portion of the conductive bump is exposed through the second passivation material.

3. The semiconductor package of claim 2, wherein the portion of the conductive bump exposed through the second passivation material is substantially flush with the second passivation material.

4. The semiconductor package of claim 1, wherein the first passivation material and the second passivation material comprise a silicon oxide material or a silicon nitride material.

5. The semiconductor package of claim 1, further comprising a third passivation material formed on the back surface of the semiconductor device.

6. The semiconductor package of claim 5, wherein the semiconductor device is substantially hermetically sealed by the first passivation material, the second passivation material, and the third passivation material.

7. The semiconductor package of claim 5, wherein the third passivation material comprises a polymer material, an epoxy material, a glass material, a silicon nitride material, or a silicon oxide material.

8. A packaged semiconductor device, comprising:

a semiconductor device having an active surface, a back side, and side edges extending from the active surface to the back side;

a plurality of bond pads on the active surface;

a first passivation material on the active surface exposing the plurality of bond pads;

a plurality of conductive bumps, one conductive bump of the plurality of conductive bumps over each bond pad of the plurality of bond pads;

a second passivation material over the first passivation material, the plurality of conductive bumps, and the side edges of the semiconductor device.

9. The packaged semiconductor device of claim 8, wherein a portion of at least one conductive bump of the plurality of conductive bumps is exposed through the second passivation material.

10. The packaged semiconductor device of claim 8, further comprising a third passivation material on the back side of the semiconductor device.

11. The packaged semiconductor device of claim 10, wherein the second passivation material on the side edges of the semiconductor device overlaps an edge of the third passivation material on the back side of the semiconductor device.

12. The packaged semiconductor device of claim 10, wherein a portion of the second passivation material on the side edges of the semiconductor device is adjacent to the third passivation material.

13. The semiconductor package of claim 8, further comprising a layer of under-bump metallization between each conductive bump of the plurality of conductive bumps and a corresponding bond pad of the plurality of bond pads on the semiconductor device.

14. A memory device, comprising:

a semiconductor device;

a first passivation material on a back side of the semiconductor device;

a second passivation material on an active surface of the semiconductor device;

a third passivation material on side edges of the semiconductor device extending from the first passivation material to the second passivation material; and

a carrier substrate electrically coupled to the semiconductor device.

15. The memory device of claim 14, further comprising an additional passivation material disposed between the active surface of the semiconductor device and the second passivation material.

16. The memory device of claim 14, further comprising a plurality of conductive bumps on the active surface of the semiconductor device.

17. The memory device of claim 16, wherein a portion of each of the conductive bumps of the plurality of conductive bumps is exposed through the second passivation material.

18. The memory device of claim 17, wherein the carrier substrate electrically coupled to the semiconductor device comprises a flip-chip arrangement wherein the plurality of conductive bumps are electrically coupled to the carrier substrate.

19. The memory device of claim 18, wherein the carrier substrate comprises a plurality of contact pads.

20. The memory device of claim 14, wherein the second passivation material and the third passivation material are congruent.