INCREASING READOUT SPEED IN CMOS APS SENSORS THROUGH BLOCK READOUT
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Abstract
A method and associated architecture for dividing column readout circuitry in an active pixel sensor in a manner which reduces the parasitic capacitance on the readout line. In a preferred implementation, column readout circuits are grouped in blocks and provided with block signaling. Accordingly, only column output circuits in a selected block significantly impart a parasitic capacitance effect on shared column readout lines. Block signaling allows increasing pixel readout rate while maintaining a constant frame rate for utility in large format high-speed imaging applications.
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Citations
79 Claims
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1-23. -23. (canceled)
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24. An image sensor, comprising:
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a pixel array comprising a plurality of pixels, organized into N selectable rows and M columns, wherein N and M are positive integers; M column output circuits, each of which can be actively coupled to pixels in the N rows in a respective column, each of said M column output circuits for respectively outputting a respective signal corresponding to a respective pixel of a selected row, said M column output circuits being organized into B blocks, B being a positive integer greater than 1, each of said B blocks comprising k of said M column output circuits, wherein k is a positive integer greater than 1 and k=M/B; B block output lines each for receiving signals from said k column output circuits of a respective block; and selection circuitry between said B block output lines and a master output line for actively coupling a single one of said B block output lines to said master output line at a time and thereby allow said k column output circuits associated with an actively coupled block output line to be actively coupled to said master output line through said selection circuitry. - View Dependent Claims (25)
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26. An image sensor, comprising:
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a pixel array comprising a plurality of pixels, organized into N rows and M columns, wherein N and M are positive integers; M output circuits, each of said M output circuits for respectively outputting a respective signal associated with a respective one of M pixels of a selected row, wherein said M output circuits are organized into B blocks, B being a positive integer greater than two, each of said B blocks comprising k of said M output circuits, wherein k is a positive integer such that k=M/B; B block output lines each coupled to said k output circuits of a respective block; a master output line; and a selection circuit, for actively coupling a single one of said B block output lines to said master output line at a time. - View Dependent Claims (27, 28, 29, 30, 31, 33)
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32. A CMOS imager, comprising:
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a pixel array comprising a plurality of pixels, organized into N rows and M columns, wherein N and M are positive integers; M column output circuits, each of which can be actively coupled to the N rows in a column, each of said M output circuits to output a respective signal associated with a respective pixel of a selected row, wherein said M column output circuits are organized into B blocks, B being a positive integer greater than two, each of said B blocks comprising k of said M column output circuits, wherein k is a positive integer greater than 1 and k=M/B; B block output lines each connected to said k column output circuits of a respective block; and a selection circuit configured to actively couple a single one of said B block output lines to a master output line at a time and thereby allow said k column output circuits associated with an actively coupled block output line to be actively connected to said master output line through said selection circuit. - View Dependent Claims (36, 37, 38, 39)
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34. A CMOS imager, comprising:
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a pixel array comprising a plurality of pixels, organized into N rows and M columns, wherein N and M are positive integers; and M output circuits, each of said M output circuits for respectively outputting signals from M pixels of a selected row; wherein said M output circuits are organized into B blocks, B being a positive integer, each of said B blocks comprising k of said M output circuits, wherein k is a positive integer such that k=M/B;
B block output lines each coupled to said k output circuits of a respective block;a master output line; and a selection circuit, for actively coupling a single one of said B block output lines to said master output line at a time. - View Dependent Claims (35)
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40. A method of reading out signals of a selected row in an imager having pixels arranged in N rows by M columns through M column output circuits, the method comprising:
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(a) operating said M column output circuits in B groups each having k column output circuits and a respective common group output line, each of said M column output circuits coupled to the N rows of a respective column; (b) actively coupling only said respective common group output line of a selected one of said B groups to a master output node to receive said signals; and (c) reading out said signals from each of said k column output circuits in the selected one of said B groups; wherein M, B, and k are integers greater than two. - View Dependent Claims (41, 42)
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43. A method of reading out pixel signals of a selected row in an imager having pixels arranged in N rows by M columns through M output circuits, the method comprising:
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(a) operating said M output circuits in B groups each having k output circuits and a common group output line; (b) selecting only one at a time of said B groups by actively coupling said common group output line of a selected group to a master output node; (c) reading out pixel signals from each of said k output circuits in the selected group; and wherein M, B, and k are integers. - View Dependent Claims (44)
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45. An imaging device, comprising:
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an array of pixels, including source follower transistors, wherein a first set of adjacent columns of pixels of the array are connected to a first set of column output lines, and a second set of adjacent columns of pixels of the array are connected to a second set of column output lines; a first set of greater than two column output circuits connected to the first set of column output lines to provide a first set of signals associated with a first set of pixels in a selected row and in the first set of adjacent columns, and a second set of greater than two column output circuits connected to the second set of column output lines to provide a second set of signals associated with a second set of pixels in the selected row and in the second set of adjacent columns; and a first block select switch connected between the first set of column output circuits and a first array readout line and a second block select switch connected between the second set of column output circuits and the first array readout line, wherein the first block select switch, when enabled, allows the first set of signals to be driven onto the first array readout line, the second block select switch, when enabled, allows the second set of signals to be driven onto the first array readout line, and the first and second block select switches are to be enabled one-at-a-time. - View Dependent Claims (46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64)
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65. A method, comprising:
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generating first signals associated with a first row of pixels of an array of pixels of a CMOS imager during a frame readout; transferring each of at least eight groups of signals selected from the first signals to a respective one of at least eight block output busses, wherein each of the groups of signals selected from the first signals are associated with adjacent pixels in the first row of pixels of the array; and transferring only a single one of the groups of signals selected from the first signals from a respective one of the block output busses to a master readout bus at a time. - View Dependent Claims (66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79)
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Specification