SEMICONDUCTOR STORAGE DEVICE AND METHOD OF OPERATING THE SAME
First Claim
1. A semiconductor storage device comprising:
- a plurality of arrays of memory cells, each memory cell including a ferroelectric capacitor and a transistor, the plurality of memory cell arrays comprising;
word lines operative to select memory cells in the array,plate lines operative to apply drive voltage to the ferroelectric capacitors in the array, anda pair of bit lines operative to read data from the ferroelectric capacitors in the array;
a selection transistor operative to selectively connect a memory cell block to one bit line of the pair of bit lines;
a dummy capacitor operative to provide a reference potential corresponding to a potential read from one of the memory cells to an other bit line of the pair of bit lines;
a sense amplifier circuit to compare and amplify potentials between the bit lines of the pair of bit lines;
a reference potential correction capacitor connected to the pair of bit lines together with the dummy capacitor; and
a control circuit configured to output a correction signal based on shift information to correct the reference potential, the shift information being retained in at least one of the plurality of memory cell arrays,the reference potential correction capacitor shifting the reference potential by changing the amount of accumulated electric charges according to the correction signal.
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Accused Products
Abstract
A semiconductor storage device includes: a plurality of memory cell arrays, each having a memory cell arranged therein, the memory cell including a ferroelectric capacitor and a transistor; a dummy capacitor operative to provide a reference potential corresponding to a potential read from the memory cell; a sense amplifier circuit including an amplifier circuit to compare and amplify potentials between a pair of bit lines; a reference potential correction capacitor connected to the pair of bit lines together with the dummy capacitor; and a control circuit configured to output a correction signal based on shift information to correct the reference potential, the shift information being retained in at least one of the plurality of memory cell arrays. The reference potential correction capacitor shifts the reference potential by changing the amount of accumulated electric charges according to the correction signal.
14 Citations
20 Claims
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1. A semiconductor storage device comprising:
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a plurality of arrays of memory cells, each memory cell including a ferroelectric capacitor and a transistor, the plurality of memory cell arrays comprising; word lines operative to select memory cells in the array, plate lines operative to apply drive voltage to the ferroelectric capacitors in the array, and a pair of bit lines operative to read data from the ferroelectric capacitors in the array; a selection transistor operative to selectively connect a memory cell block to one bit line of the pair of bit lines; a dummy capacitor operative to provide a reference potential corresponding to a potential read from one of the memory cells to an other bit line of the pair of bit lines; a sense amplifier circuit to compare and amplify potentials between the bit lines of the pair of bit lines; a reference potential correction capacitor connected to the pair of bit lines together with the dummy capacitor; and a control circuit configured to output a correction signal based on shift information to correct the reference potential, the shift information being retained in at least one of the plurality of memory cell arrays, the reference potential correction capacitor shifting the reference potential by changing the amount of accumulated electric charges according to the correction signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A semiconductor storage device comprising:
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a plurality of memory cell arrays, each having memory cells and a pair of bit lines arranged therein, each memory cell including a ferroelectric capacitor and a transistor, the pair of bit lines operative to read data from the ferroelectric capacitor of the memory cells; a dummy capacitor operative to provide a reference potential corresponding to a potential read from the memory cells to the pair of bit lines; a reference potential correction capacitor connected to the pair of bit lines; and a sense amplifier circuit including an amplifier circuit to compare and amplify potentials between the pair of bit lines, wherein when a potential read from the memory cell is provided to one bit line of the pair of bit lines, the reference potential correction capacitor shifts the reference potential provided to an other bit line of the pair of bit lines. - View Dependent Claims (12, 13, 14, 15)
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16. A method of operating a semiconductor storage device, the method comprising:
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reading data from a ferroelectric capacitor of a memory cell to one bit line of a pair of bit lines, the memory cell including the ferroelectric capacitor and a transistor and being arranged in each of a plurality of memory cell arrays; providing, by a dummy capacitor, a reference potential corresponding to a potential read from the memory cell to an other bit line of the pair of bit lines; outputting, by a control circuit, a correction signal based on shift information to correct a reference potential, the shift information being retained in at least one of the plurality of memory cell arrays; shifting, by a reference potential correction capacitor connected to the pair of bit lines, the reference potential by changing the amount of accumulated electric charges of the correction signal; and comparing and amplifying, by a sense amplifier circuit, potentials between the pair of bit lines. - View Dependent Claims (17, 18, 19, 20)
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Specification